Electronic – Testbench for INOUT port in VHDL

fpgaportsimulationvhdl

I was looking in the internet and stackexchange for the solution but still I don't know why it is not working. Solutions which I found here shall work but probably I am still doing something wrong.

I am writing VHDL 'code'. I have in my design INOUT ports. In libero soc synthesis and compilation works fine. Now I would like to simulate my design and here is the problem. I am using Mentor Graphics ModelSim. During compilation testbench I have an error

Nonresolved signal 'data' has multiple sources.

architecture architecture_max11046_interface_tb of max11046_interface_tb is

component max11046_interface is
    port (
        -- Clock and resets
        i_clk           : in std_ulogic;
        i_rst_asyn      : in std_ulogic;
        i_rst_syn       : in std_ulogic;

        -- Max11046 interface
        o_cs        : out std_ulogic;
        o_wr        : out std_ulogic;
        o_rd        : out std_ulogic;
        o_convst    : out std_ulogic;
        o_shdn      : out std_ulogic;
        i_eoc       : in  std_ulogic;
        io_data      : inout  std_ulogic_vector(15 downto 0)
    );
end component;


-- input signals
signal eoc:    std_ulogic := '1';
signal data:   std_ulogic_vector(15 downto 0) := x"ABAB";

-- signals
signal rst: std_ulogic := '0';
signal clk: std_ulogic := '0';

signal ADC_Data: std_ulogic_vector(15 downto 0);
begin
    Conversion_end: process
    begin
        wait until convst = '1';
        wait for 500 NS;
        eoc <= '0';
    ADC_Data <= x"ABCD";
        wait for 50 NS;
        eoc <= '1';
    end process;

    data <= ADC_Data when eoc = '0' else (others => 'Z');        

    max11046: max11046_interface
        port map (
            i_clk       => clk,
            i_rst_asyn  => '1',
            i_rst_syn   => rst,
            o_cs        => cs,
            o_wr        => wr,
            o_rd        => rd,
            o_convst    => convst,
            o_shdn      => shdn,
            i_eoc       => eoc,
            io_data      => data
        );

 end architecture_max11046_interface_tb;

I've deleted some part of code to make it easier to read. My question is what can be wrong. Can not I drive internal signal from multiple sources ? In the design I am doing it like this with ports and it is working:

data <= ADC_Data when eoc = '0' else (others => 'Z');

when i am not writing to the port it is in high impedance and i can read data.

P.S. I don't want to use std_logic_vector instead of std_ulogic_vector.

Best Answer

You're trying to create a tri-state signal on 'data' of unresolved type std_ulogic_vector. The 'unresolved' means that it doesn't use a resolution function when establishing the value of a signal (i.e. a 'signal' or 'port').

A resolution function takes the value from each of the sources onto a signal and resolves them all into a single assignment value.

So the unresolved datatype you have selected only allows one source, by definition. The solution is to use a resolved type because they deal with multiple sources onto a single signal, which is what you wanted to implement.

The typical resolved types here are std_logic and std_logic_vector instead. (You don't explain why you don't want to use them, only that you don't.)

Incidentally, the initial values on your signals don't constitute another source. They're just values your simulator will start off with in the signals. In their absence, your simulator would put 'U's on the signals you have.

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