Electronic – VHDL: Signal vs Port

If you are wondering about how the <= operator works; it is what is called a 'nonblocking assignment.' What this means is that the left hand side of all of the <= are performed for a particular event (e.g. rising clock edge) and then once those are all evaluated, the result is placed in the output. This allows you to write shift registers without temporary variables. None of the values change until the left hand calculations are completed, then the results are moved over to the right hand side. It is generally not a good idea to use nonblocking assignments for combinatorial logic. Generally they are only used to create latches and registers and you use regular blocking assignments for combinatorial logic. When synchronized with a clock signal, you can generally consider <= operations to be D flip-flops that sample the input and transfer it to the output atomically on a single clock edge.

'Race conditions' where intermediate indeterminate results appear on the outputs of combinatorial functions are hard to avoid and they can depend greatly on how the design is actually implemented on an ASIC or FPGA. However, most designs are synchronous and so as long as the output settles within one clock period this is not a problem. There are tools that can check the timing performance of a design to check all of the path delays to ensure that the results will always be valid for a given clock frequency, but this is highly dependent not on the actual HDL code but on the way the design is placed and routed.

Synthesizers (not compilers!!!!) will generally perform optimization on combinatorial logic. There are limits to how much the synthesizer can do (e.g. it will not re-architect your system) so you have to know more or less how it will end up being implemented. If you're working on an FPGA, generally the synthesis and place and route will pack any logic function that fits onto LUTs. So if you can separate out a single logic function with up to 4 inputs and 1 output, this will end up on a single LUT and the only delay that matters is the propagation delay of the LUT, which is the same for all of its inputs. In the case of your example function, both pieces of code may be implemented identically on one LUT with three inputs and one output.

You're trying to create a tri-state signal on 'data' of unresolved type std_ulogic_vector. The 'unresolved' means that it doesn't use a resolution function when establishing the value of a signal (i.e. a 'signal' or 'port').

A resolution function takes the value from each of the sources onto a signal and resolves them all into a single assignment value.

So the unresolved datatype you have selected only allows one source, by definition. The solution is to use a resolved type because they deal with multiple sources onto a single signal, which is what you wanted to implement.

The typical resolved types here are std_logic and std_logic_vector instead. (You don't explain why you don't want to use them, only that you don't.)

Incidentally, the initial values on your signals don't constitute another source. They're just values your simulator will start off with in the signals. In their absence, your simulator would put 'U's on the signals you have.