Electronic – the standard way to halt a VHDL testbench after a certain time period

digital-logicsimulationvhdl

In Verilog I can use the $finish function to halt the simulation, but my search for the similar option in VHDL has failed so far.

The closest solution that I found online is to use this code in my VHDL testbench:

stop_simulation :process
begin
   wait for 1000 ns; --run the simulation for this duration
   assert false
       report "simulation ended"
       severity failure;
end process ;

How do you set the time for your simulation in VHDL? For example if I want my clock to run for 10 us, then what is the STANDARD option to achieve this?

Best Answer

Two ways are commonly used:

Stop the clock (or clocks). That way there are no more events, and the simulation stops. Sometimes, there is a signal (for instance called done) that turns of the clock generator. The testbench asserts the done signal when all tests are completed.

Report a failure. This is not so elegant, but many people use it. A severity of failure will cause the simulator to stop. report "simulation finished successfully" severity FAILURE;

Stop procedure A third way, only available since VHDL 2008 is to call the procedure stop, in the env package of the std library. For instance, like this: std.env.stop;

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