Electrical – What does grey dots represent in Proteus and why I am getting those

To make a T flip-flop, you take a D-flip flop and add feedback from the output to determine the next state.

The immage bellow shows the most basic operating logic of a T flip-flop. If you removed the feed back from Q and Q' you get a D flip-flop (And I know, you also have to invert the bit input on the lower and gate. Lets keep it simple, ok?)

So when you go to use a D flip-flop in a counter circuit instead of a T flip-flop, you have to manually add in the feedback that is now missing.

Internally, a flip-flop (the term includes everything from simple D latches to more complex edge-triggered J-K master-slave flip-flops) is an asynchronous state machine. It is created by combining ordinary logic gates with feedback.

For example, here's one way to construct a master-slave D flip-flop:

^{simulate this circuit – Schematic created using CircuitLab}

Each of the internal sections is a simple set-reset latch with an enable input. Because the two enables are driven with opposite levels of the "CLK" input, the output can only change state on its rising edge.

Note that while this design is conceptually simple to understand, it is NOT typical of how commercial chips (e.g., 7400-series) are constructed internally. If you study SSI/MSI databooks (the older TI books were especially good), you'll see several other ways to construct flip-flops from gates.

Once you have an edge-triggered flip-flop of any sort, you can use it (or multiple copies of it) to create synchronous state machines that only make transitions on clock edges.