I know it's a bit late, but I've just got this sabe doubt. After looking around, I've come across this Microchip Doc that shows some examples.

First, we calculate \$\text{PR2}\$. From this formula,

$$ F_\text{PWM} = \dfrac{1}{(\text{PR2} + 1) \times 4 \times T_\text{OSC} \times \text{T2CKPS}} $$

we get

$$ \text{PR2} = \dfrac{1}{F_\text{PWM} \times 4 \times T_\text{OSC} \times \text{T2CKPS}} - 1 $$

where \$T_\text{OSC} = 1/F_\text{OSC}\$, and \$\text{T2CKPS}\$ is the Timer2 prescaler value (1, 4 or 16).

Therefore, if we want \$F_\text{PWM} = 20\text{kHz}\$, and choosing \$\text{T2CKPS} = 1\$, we get \$\text{PR2} = 249\$. We should choose higher values for \$\text{T2CKPS}\$ only if \$\text{PR2}\$ exceeds 8 bits (\$\text{PR2} \gt 255\$) for the given prescale.

Now we calculate the max PWM resolution for the given frequency:

$$ \text{max PWM resolution} = \log_2(\;\dfrac{F_\text{OSC}}{F_\text{PWM}}\;) $$

That gives us \$9.9658\$ bits (I know, it sounds weird, but we'll use it like that later).

Now, let's calculate the PWM duty cycle. It is specified by the 10-bit value \$\text{CCPRxL:DCxB1:DCxB0}\$, that is, \$\text{CCPRxL}\$ bits as the most significant part, and \$\text{DCxB1}\$ and \$\text{DCxB0}\$ (bits 5 and 4 of \$\text{CCPxCON}\$) the least significant bits. Let's call this value \$\text{DCxB9:DCxB0}\$, or simply \$\text{DCx}\$. (x is the CCP number)

In our case, since we have a max PWM resolution of \$9.9658\$ bits, the PWM duty cycle (that is, the value of \$\text{DCx}\$) must be a value between \$0\$ and \$2^{9.9658} - 1 = 999\$. So, if we want a duty cycle of 50%, \$\text{DCx} = 0.5 \times 999 = 499.5 \approx 500\$.

The formula given on the datasheet (also on the linked doc),

$$\text{duty cycle} = \text{DCx} \times T_\text{OSC} \times \text{T2CKPS}$$

gives us the pulse duration, in seconds. In our case, it's equal to \$25\text{ns}\$. Since \$T_\text{PWM} = 50\text{ns}\$, it's obvious that we have a 50% duty cycle.

That said, to calculate DCx in terms of duty cycle as \$r \in [0,1]\$, we do:

$$ \text{DCx} = \dfrac{r \times T_\text{PWM}}{T_\text{OSC} \times \text{T2CKPS}} = \dfrac{r \times F_\text{OSC}}{F_\text{PWM} \times \text{T2CKPS}} $$

Answering your other questions:

2) The resolution of your PWM pulse with period \$T_\text{PWM}\$ is

$$ \dfrac{T_\text{PWM}}{2^\text{max PWM res}} $$

3) Because CCPRxL, along with DCxB1 and DCxB0, determine the pulse duration. Setting CCPRxL with a higher value than \$2^\text{max PWM res} - 1\$ means a pulse duration higher than the PWM period, and therefore you'll get a flat \$V_{DD}\$ signal.

## Best Answer

A register is characterized by a

setup time\$t_s\$ and ahold time\$t_h\$. These define a window around the clock event during which the input signals must be stable for the register to be guaranteed to work as expected.If the clock event happens at time \$t_c\$, the input signal must be at the desired new value before \$t_c-t_s\$, and it must maintain that value until at least \$t_c+t_h\$. If this is done, then the new value of the output after the clock event will be as expected. If the input value changes during the window \$t_c-t_s < t < t_c+t_h\$, then it is uncertain what the new output value will be, and the register may even enter a

metastable statewhere its output doesn't take a legal logic level.(source)

Any control signals such as LOAD and synchronous SET or RESET inputs must meet setup and hold time requirements in exactly the same way as the data input must.

As a side note, it's also common in FPGAs for \$t_h\$ to be negative, so the entire timing window occurs before the clock event (by at least a few picoseconds). This ensures that when one register feeds another, changing the output of the first register doesn't violate the hold time requirement of the next register.