Control Signal Timing for Register Update – How to Ensure Proper Load


I know this is a pretty basic question, but I didn't succeed to find an unambiguous answer.
Does a register need to get load signal in the cycle in which the new value computation is made? or at the beginning of the next cycle? Ill give an example to make my question clearer:

lets assume I want to increase PC (program counter register) value by 4 every cycle. In t0 the initial PC value is been transmitted to an adder, which calculate PC+k and is connected back to the PC's entrance. In order that in the next clock t0+Tclock the PC value will be updated to it's new values PC+k , does the controller should have sent a Load signal in t0 or it should sent a Load signal in t0+Tclock (the next clock)?

Best Answer

A register is characterized by a setup time \$t_s\$ and a hold time \$t_h\$. These define a window around the clock event during which the input signals must be stable for the register to be guaranteed to work as expected.

If the clock event happens at time \$t_c\$, the input signal must be at the desired new value before \$t_c-t_s\$, and it must maintain that value until at least \$t_c+t_h\$. If this is done, then the new value of the output after the clock event will be as expected. If the input value changes during the window \$t_c-t_s < t < t_c+t_h\$, then it is uncertain what the new output value will be, and the register may even enter a metastable state where its output doesn't take a legal logic level.

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Any control signals such as LOAD and synchronous SET or RESET inputs must meet setup and hold time requirements in exactly the same way as the data input must.

As a side note, it's also common in FPGAs for \$t_h\$ to be negative, so the entire timing window occurs before the clock event (by at least a few picoseconds). This ensures that when one register feeds another, changing the output of the first register doesn't violate the hold time requirement of the next register.