I am trying to use the SPI0 component of a Zynq XC7Z010 to read data from a 12-bit rotary encoder which uses an SSI protocol.
- I have a small example project set up in Vivado which enables the SPI0 to use EMIO ports and sets the pins I want to use.
- I also have the xspips driver working and am able to receive data from the encoder.
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The problem I am facing is that I could only set up a clock signal which is idle low, while the encoder expects an idle high clock.
- Due to this, the first bits received are unusable, and I had to do some bit-manipulation to recover these bits (the encoder starts repeating the same data again after the 12 bit transmission).
With an oscilloscope I tested out that the sent out clock signal is always idle low, whether the CLK_ACTIVE_LOW option is set or not for the SPI, so I concluded that that option is only for how the Zynq interprets the clock signal.
How can I have a clock signal that is high by default? Do I have to manually invert it in the Vivado generated VHDL wrapper, or is there a simpler solution?
Measured clock signal for a 2 byte transfer when ACTIVE_LOW is enabled:
and when it is disabled:
Best Answer
Your first oscilloscope trace (ACTIVE_LOW enabled) seems to show the clock going high-Z when idle. Note the slow decay. Try adding a fairly week pull-up resistor to the clock line, maybe 10K, and I think you'll ge what you want.