Electronic – 2C Master Stretch the clock

i2c

The I2C manual by NXP allows Clock Stretching (holding SCL low) by slave devices in order to have the master wait for them to process data, interrupts and the like. This is all fine and well, although not having a timeout seems questionable.

Now, I wonder whether a master controller can use the same method for example when waiting for the host processor to provide/collect data. For simplicity I only consider a single master setup, although it should not matter.

Edit: For the sake of clarity I am concerned about cases in which during a multi-byte transfer the host processor is not able to provide/collect data to/from the master controller. Issuing a STOP and possibly resetting the slave's state machine (auto-increment counters, 32-bit internal registers, etc.) is not feasible.

Best Answer

Being the master the clock generator, it's in fact reducing the clock frequency by its own, contrary to a slave, that has the clock generated by the master, but wants to signal the master to hold it.

According to Wikipedia:

Although the master may also hold the SCL line low for as long as it desires, the term "clock stretching" is normally used only when slaves do it.

But

To ensure a minimum bus throughput, SMBus places limits on how far clocks may be stretched. Hosts and slaves adhering to those limits cannot block access to the bus for > more than a short time, which is not a guarantee made by pure I²C systems.

So, when using clock stretching be sure the devices support it, as for trademark reasons I2C is implemented as other names and has not all features. But that is more a concern for slave devices.

Related Solutions

Electronic – i2c automatic address assignment

Your problem can be solved with SMBus which is logically an extension on I2C. SMBus supports an ARP, wherein it can detect multiple IC's of same address, and assign them a different address. The ARP process basically reads a UUID ( a unique id per device; all the different devices in the same lot will have a different UUID) from the slave address (there may be multiple devices on this slave address). Due to the I2C bus arbiration process, only one slave will succeed at a time, and the master successfully reads its UUID. Then the master assigns a unique address using that UUID as reference. The process is repeated until all the slaves get a resolved address.

Electronic – How is the clock frequency established between master and slave in I2C protocol

Following up the comments:

Yes, the frequency is hard-coded into some specific I2C-related registers. At runtime.

That said, your Arduino library might be doing some probing and rise time measurement on the bus for determining a viable clock rate. Let's see.

After doing a bit of source-digging, the answer is in twi.h

#ifndef TWI_FREQ
#define TWI_FREQ 100000L
#endif

Another piece from that very file:

TWBR = ((CPU_FREQ / TWI_FREQ) - 16) / 2;

Where TWBR stands for Two Wire Baudrate Register I suspect.

I'd call that enough evidence and definitely say, yes your I2C frequency is set directly by your library without any negotiations. If you want to change it, I'd suggest you #define TWI_FREQ before you #include twi.h (or indirectly through Wire.h)

Best Answer

Related Solutions

Electronic – i2c automatic address assignment

Electronic – How is the clock frequency established between master and slave in I2C protocol

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