Multiplexer – 32 Bit, 4 Way Multiplexer Design

Do these cartridges have any kind of "cartridge select" pin? If so, you could conceivably connect all the lines except for the select in parallel and just drive the appropriate select line.

If they don't have a select line, do the cartridges have any address(es) which cause the data lines to be released/"driven" to high impedance? If so, do the cartridges have a common address for all of the cartridges which do this? If they do, there's your cartridge select -- connect the data lines in parallel and connect as many address lines in parallel as you can; that gives you fewer lines you have to multiplex.

Failing all of that, you're stuck with a high pin count FPGA to do it, which is probably your best solution. I think that no matter what you'll want to go through the above exercises to minimize the number of uniquely driven lines. It sounds like an interesting project. Good luck!

First, presumably you've already looked at assigning channels by geometric convenience rather than number and decided that doesn't solve your problem.

A CPLD could give you a lot of pinout flexiblity, but perhaps would be "cheating" by your goals (though there were board-level mainframe CPUs that used early PALs).

On the novel front, if your delay budget is generous an (E)PROM loaded with a suitable truth table to use address lines as channel and select inputs could be a solution. Perhaps you are already using something similar to hold a table for instruction decode or even microcode.

A more off-the-shelf solution might be to use tri-state buffers on each side, with only one enabled at a time, or even at an extreme, open-collector logic gates and a pullup.