I need to design a 4-input sequence detector and I'm really having trouble with this.
The numbers are entered as a 4 digit input (0010 is 2, 0110 is 6, etc).
The sequence must detect, for instance, a 5 digit key (i.e 3-4-1-7-5)
I'm really troubled with the design methodology for this problem, because if we do it the traditional way, it's going to take forever, we need 3 state variables and 11 different inputs possibilities to deal with (the 1010 key is "clear")
If we type 3-4-4, the sequence must clear, for example.
If we type 3-4-1-7-5 (the correct sequence), then the output should be a logical 1.
Otherwise, the output is zero.
Any help greatly appreciated.
EDIT: the sequential circuit is synchronous (has an external clock source)
Best Answer
Here's a hint: The states in your state machine are not associated with the binary codes representing the key inputs, they're associated with the number of correct numbers entered so far. You start out in an initial, or "reset" state, in which no valid keys have been entered so far, and then proceed to states representing 1 valid key entered, 2 valid keys entered, etc. until you get to the final state with 5 valid keys entered. In the last state, the output is 1; in all others it's 0.
In each state, if the next valid key is entered, you proceed to the next state; otherwise, you go back to the initial state.