555edgetrigger
Is there a circuit using the 555 (without additional logic gates) that creates a positive pulse when it detects a rising or falling edge?
The goal is to have a circuit that detects when a signal goes from
5v –> 0v & 0v –> 5v. When an edge accrues it outputs a (preferably) positive pulse.
I'm assuming you don't want to use a microcontroller for this, so here's a 555/logic based idea:
Disclaimer: I threw this together in 5 mins, and haven't used a 555 timer for ages, so I may have made a mistake (or three)
Anyway, the basic idea is simple, set the 555 up in monostable "one-shot" mode, and use an inverter gate and a couple of caps/diodes to produce negative pulses on ignition on/off. The inverter gate can be anything that has a reasonably low output impedance.
The inverter power pins are not shown, and ignore R3 (it's just there for SPICE simulation purposes)
Here's simulation of the circuit (on/off time of ignition shortened from "normal" use)
The ignition starts the simulation on, turns off at 1 second, and turns on again at 11 seconds, each time producing a 3 second pulse at the 555 output (this can be used to drive a transistor to switch your GoPro):
A CD4098 dual one-shot will meet all your stated requirements and is very cheap and available. It can operate from 9V, trigger on either the rising or falling edge, and provides positive or negative going pulses. An R-C pair sets the pulse duration for each half of the chip.
Best Answer
Sorry about the non optimized circuit and the disorder: I can't figure out how to reorder the terminals of 555.
The circuit works as follows.
Let's assume that C3 is charged. (if it were discharged, the trigger input would bring the output pin high, which would quickly charge C3).
Therefore, in DC conditions, trigger input is high (not active), output is high (as said before), reset is high, discharge is high (due to the pull-up resistor R3), and the threshold input is low. The internal flip flop is therefore in the set state. Suppose that V1 was low. C1 is positively charged (considering the voltage Vleft-Vright), while C2 has 0 voltage.
When V1 goes high, D1 protects the reset input (it clamps the reset voltage so that it does not go too high with respect to VCC). The thresold voltage goes high (time constant: R1 * C1), so the output node goes low, allowing C3 to discharge through R2. In the meantime, discharge goes low. Once C3 goes below VCC/3, the output will become high (quickly charging C3) and discharge again is low.
When V1 goes low, D3 protects the threshold input (it clamps the threshold voltage so that it does not go too low with respect to GND). The flip flop is resetted again, because reset also goes low for a brief moment (time constant: C2 * R4). Therefore, again the output goes low, etc.
If you want a positive pulse (instead of a negative) add a NPN transistor. Connect the base to the "discharge" pin (it is open collector).
Adjust the time constants as desired for your operation.
simulate this circuit – Schematic created using CircuitLab