Electronic – 8-bit per cell memory

It's not clear what you are really asking, but it is common to store binary values that are wider than the addressable unit of memory. For example, if you want to store 16 bit words in a byte-addressed memory, then you use two bytes. That also means the software has to know which byte is stored first.

In your case you seem to have native 4 bit words. To store a 16 bit value, use 4 words. Again, your software will have to know what convention you are using, like low word first or high word first.

Since your memory only has 4 address lines, its size is limited to 16 native words. Your native word size appears to be 4 bits, so your memory can hold only 64 bits. That means it will be completely used up by two 32 bit values or four 16 bit values, for example.

A 32 or 64 bit processor differs for its ability to allocate 2 ^ 32 or 2 ^ 64 addresses for the cells of the RAM.

Basic assumption is wrong there. A 32-bit CPU operates natively on 32 bits of data at a time. That is, the internal registers and data pathways are in blocks of 32, so each register has 32 bits, and data is moved around in chunks of 32 bits. With a 64-bit CPU it is 64 bits per register and data is moved around in chunks of 64 bits.

It is often the case that the address bus is the same size as the internal native architecture purely because that's convenient. However, it is not always the case. Take the Z80 CPU. It's an 8 bit CPU, yet it has a 16 bit address bus.

One memory "cell" contains either a 1 or a 0. It is one bit. They are grouped into words of whatever the memory interface is, and you access the memory either as whole words, or in the case of a number of chips, as portions of words (many chips have the ability to "mask" the data to work with just an upper or lower byte, say).

Seen from the CPU's perspective a word is the width of its internal architecture, so a 32-bit CPU works with 32-bit words. From the RAM chip's perspective a word is the size of its data interface, so a 16-bit RAM chip has 16-bit words.

For the best efficiency you want to match the CPU's architecture size and the RAM's bus width. That could be done either with a 32-bit CPU and 32-bit RAM, or more commonly, by adding multiple RAM chips in parallel, for example a 64-bit CPU and four 16-bit RAM chips - each RAM chip handling a quarter of the data lines.