Everything you need is in the datasheet for that chip in table 4-2 and 4-4. There is no 17 bit mode, but a twos-complement 18 bit mode. If your gains are set to 1, then
Vref- 1LSB will produce 0b01 1111 1111 1111 1111
-Vref will sample as 0b10 0000 0000 0000 0000
and zero will be all zeros
You must divide Vref by any gain setting other than one you place on the PGA.
Having an 18 bit word come in via I2C means that you'll either be throwing out some LSB's, of reading the data into a 32 bit word. Pay very close attention to pages 23 and 24 so you understand what your data will look like. Since these are twos complement numbers, I recommend SOMEHOW reading them in such that the data is LEFT ALIGNED with your SIGNED 32-bit word, and then you can shift them right if you prefer them right aligned, and the compiler should not have problems dealing with the twos complement format. Note that if you get dealing with twos complement format wrong any numbers that end up negative (even due to noise) will not be handled correctly.
If you wish to have the same number of samples per second, then you will need to peruse the datasheets very closely. What you specifically mean by 'simultaneously' needs clarification. All I can show you here is how to achieve correlated samples at the same rate.
The ADS1158 shows (datasheet figure 128) shows a fixed channel mode at its simplest with the data rate at Fclk/128. This appears to be the sample rate.
The ADS1191 is optimised for sample rates of <=8kS/s. Using the 8kS/s rate would therefore be the best you can achieve, according to the manufacturer.
There is an option for an external clock on both, so lets see what you can do.
The ADS1191 accepts a 2.048MHz clock (see the datasheet for details of pin connections as the modulator is expected to run at 128kHz).
To get the 8kS/s rate from the ADS1158 in the simple mode above, yields a master clock of 1.024Mhz. Note that there are limited options to change the sample rate in this part
This is fortunate: Generate a master 2.048MHz clock for the ADS1191 and divide it by 2 to yield the external clock on the ADS1158.
If you now start each conversion at the same instant, you will get conversions that take the same amount of time, and the sample rate is correlated.
Note that the 2.048MHz clock for the ADS1191 was only implemented to enable faster SPI access - you should not attempt to run the modulator above 128kHz.
[Update in response to comment]
I suggested a master clock because that was one method of achieving the desired result; as you note, there are other methods.
A D type flip flop with #Q to D is indeed a standard way to divide a clock by 2.
HTH
Best Answer
In the case of a successive approximation converter, it will perform one conversion step per clock cycle, which actually performs one bit of the conversion. Thus an 8-bit conversion takes at least 8 clock cycles ( 4 us) and a 10-bit conversion takes at least 10 cycles (5 us) with a 2 MHz conversion clock (0.5 us period)
In the first step it performs the MSB conversion, asking "is the value more than half the reference voltage?", setting the MSB to '1' if yes, and subtracting either half the reference or zero (accordingly) from the input value.
In the next step it converts the next bit, asking "is the remaining value more than 1/4 the reference voltage?" and so on for each bit.
There is also some overhead, for tasks like storing the final result from the conversion into the output register, resetting the internal circuitry, and "freezing" the analog value for the next conversion (in a "sample and hold" circuit) to keep it stable during the actual conversion.
The designers of you example converter apparently decided to use 4 additional clock cycles for these tasks, thus giving 6us and 7us total time for a conversion.
There are ADCs which can perform an entire conversion in a single clock cycle, these are known as "flash" converters.