Electronic – Adjustable Clock Generator between 15.5 MHz and 17.4 MHz

Code Examples

Hop over to OpenCores and you will find dozens of open source projects. There are many written in Verilog and cover the gamut from I/O devices through to processors.

Also, do not forget the many Application Notes available from Xilinx. They are very helpful with their own devices.

Design Flow

Pick up a book or two on design flow so that you get an overview on the steps involved in FPGA design. In summary, they will involve:

1. Design entry - in your case, Verilog.
2. Functional simulation - using various tools.
3. Synthesis - in your case, using the Xilinx ISE tools.
4. Simulation - to verify your post-synthesis design because some aspects of Verilog are not synthesisable.
5. Place & Route - using the Xilinx ISE tools.
6. Implementation - downloading the design onto the FPGA.
7. Testing.

FPGA Components

As for using the FPGA components, there are different ways to use them. But assuming that you are using a Verilog design entry, you can either infer or instantiate the different components.

Inference generally involves getting the synthesis tool to pick the best components to use based on the functionality that you require. The best example of this would be to design an adder.

By doing q <= a + b or q = a + b you can infer an adder. Both will infer the adder but there is a difference in when you use the blocking/non-blocking syntax.

Instantiation generally involves calling the exact library component in code. Some components just cannot be easily inferred in code - such as the DCM. You can use the ISE tools and examples to learn more about this.

The actual list of components themselves are provided by Xilinx in the Libraries Guide.

Protip

The best way to learn this is actually to experiment with short bits of code and run them through the ISE synthesis to see what it spits out. There are also plenty of examples in the ISE toolset itself.

Your design will not function correctly if it runs at 100 MHz but is only spec'd (by the tools) to run at 50 MHz. If it does, then it's a one-off miracle that wouldn't work when you make a change and rerun the tools. Don't do it. Don't even do it if your clock is 100 MHz and the tools tell you the design can run at 99.5 MHz.

To solve your problem you can either write a simple 'divide by power of 2' clock divider to reduce the clock frequency (something like this in Verilog):

reg [n:0] count; 

always @(posedge CLK_100) begin
  count <= count + 1;
end

BUFG bg_0 (.I(count[m]), .O(CLK_DIV));

(where 'm' <= 'n' and 'bufg' is a global clock buffer, and must be used for synchronous designs) or use a Digital Clock Manager (DCM).

Hopefully that solves your pipelining issues as well unless you absolutely have to run the entire design at 100 MHz. Other than pipelining you can consider using FIFOs if you have part of the design running at 50 MHz and the other at 100 MHz, but you'll have to say a bit more about what you're doing to get more meaningful help here.