If you want affordable boards, forget about blind vias, via in pad, and filled vias. This is a good presentation on BGA routing, albeit for very high-density boards, but the basic principles will be the same for less demanding layouts.
SMD pads vs NSMD pads is something you need to ask the company doing your BGA assembly about. The latter seems to be preferred. Some chip manufacturers have recommendations, as well.
If you have questions, this forum is very useful. You can also learn a lot by reading the various posts.
Your placement is fine.
Your routing of the crystal signal traces is fine.
Your grounding is bad. Fortunately, doing it better actually makes your PCB design easier. There will be significant high frequency content in the microcontroller return currents and the currents thru the crystal caps. These should be contained locally and NOT allowed to flow accross the main ground plane. If you don't avoid that, you don't have a ground plane anymore but a center-fed patch antenna.
Tie all the ground immediately associated with the micro together on the top layer. This includes the micro's ground pins and the ground side of the crystal caps. Then connect this net to the main ground plane in only one place. This way the high frequency loop currents caused by the micro and the crystal stay on the local net. The only current flowing thru the connection to the main ground plane are the return currents seen by the rest of the circuit.
For extra credit, so something similar with the micro's power net, place the two single feed points near each other, then put a 10 µF or so ceramic cap right between the two immediately on the micro side of the feed points. The cap becomes a second level shunt for high frequency power to ground currents produced by the micro circuit, and the closeness of the feed points reduces the patch antenna drive level of whatever escapes your other defenses.
For more details, see https://electronics.stackexchange.com/a/15143/4512.
Added in response to your new layout:
This is definitely better in that the high frequency loop currents are kept of the main ground plane. That should reduce overall radiation from the board. Since all antennas work symmetrically as receivers and transmitters, that also reduces your susceptibility to external signals.
I don't see the need to make the ground trace from the crystal caps back to the micro so fat. There is little harm in it, but it is not necessary. The currents are quite small, so even just a 8 mil trace will be fine.
I really don't see the point to the deliberate antenna coming down from the crystal caps and wrapping around the crystal. Your signals are well below where that will start to resonate, but adding gratuitous antennas when no RF transmission or reception is intended is not a good idea. You apparently are trying to put a "guard ring" around the crystal, but gave no justification why. Unless you have very high nearby dV/dt and poorly made crystals, there is no reason they need to have guard rings.
Best Answer
Assuming you don't have access to the Altium forums. So here's what I posted there:
You basically have two options:
1: Setup your rules and decide how your testpoints will look like (you need to setup two distinct rules; Testpoint Style and Testpoint Usage): Then you can use the testpoint manager to assign testpoints automatically to Vias or Pads, basically stuff that is already there and doesn't have soldermask on top).
Although this would be the fastest approach, in the past, we've had difficulties with this approach since many of our machines during production need to actually have a "component" handle to be able to handle these testpoints. Even if we got all testpoints via the testpoint report we didn't know which net was assigned. Also, we wanted to have full control over testpoint placement. Therefore, we're doing it by hand in the following way:
2: Use a component (e.g. a small circle with a dummy pin) on your schematic, as a footprint create a dummy footprint with a pad, sized 0.3mm (or whatever size you need; also make sure to remove paste) and assign that footprint to your schematic symbol. The "Pad" will make sure that there is no solder mask at that specific position.
I attached two example files for #2 to this post.
I would highly recommend using #2 for your designs, yet this opinion is based on our experiences at our company :-)
I uploaded example files for approach #2 here: http://1drv.ms/1MQwcg6.
In case you do have access, this is the thread: https://forum.live.altium.com/posts/211923