Electronic – Altium clearance between different layers to control crosstalk /capacitance

Fundamentally, polygons are evaluated separately in the DRC system.

Traces are traces, and polygons are polygons. The DRC system for checking trace width runs effectively with the polygons all shelved.

Realistically, when would you ever want to have traces that violate the design rules? If they're embedded in a polygon to the point where their width is irrelevant, you can delete them. If they're not embedded in a polygon to the point that their width is irrelevant, their width is relevant.

You're doing something that does not make sense, and the DRC doesn't account for it because there is no reason to do what you are doing.

Unless things have changed recently it's set by the clearance design rules. I have no idea what happens if there is no applicable clearance rule but it wouldn't surpise me if it chooses to use a very small clearance.

I usually set a clearance rule specifically for polygons (use "inpolygon" in the query for one of the objects) to give the clearance I want arround polygons, often quite a bit higher than what I use as my regular clearance rule.