Electronic – Why polygon pour size and trace width don’t influence each other in altium

altiumtrace

Im using some thin traces in certain areas of the board that I want to have beefed up with a polygon pour. However, when I run the rule check it just ignores that the width of the traces is now effectively larger due to the pour, and still reports that they don't meet the minimum width. Is there a way to change some of the rules so that it doesn't do this?

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Here's a picture for reference. The wire inside the black rectangle highlighted green due to breaking a rule is of the same net as the polygon surrounding it.

Best Answer

Fundamentally, polygons are evaluated separately in the DRC system.

Traces are traces, and polygons are polygons. The DRC system for checking trace width runs effectively with the polygons all shelved.

Realistically, when would you ever want to have traces that violate the design rules? If they're embedded in a polygon to the point where their width is irrelevant, you can delete them. If they're not embedded in a polygon to the point that their width is irrelevant, their width is relevant.

You're doing something that does not make sense, and the DRC doesn't account for it because there is no reason to do what you are doing.