Well, this is a toughie — though fairly simple. Does anyone have experience with board twist affecting your circuit?
We have a board design that is supposed to measure a loadcell. We have finally tracked a system accuracy fault down to the amp IC. When we twist the board, the amp IC changes its output.
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Added RM:
Circuit:
Gain is 100,000 / R7 =~ 454.5 according to datasheet p15.
I get +80mV when I twist the board from its 4 corners. I'm using the amount of twist that I use to unlock my car with my car key. I get -80mV when I twist the other way. The amount of twist is proportional to the variance in output voltage.
Alternatively, if I put, say, typical pencil pressure on the top of the IC, I get +20mV. This is the most sensitive corner of the IC near pin 1.
To isolate the amp circuit, I have shorted its input and disconnected other circuits from it so that what you see in the diagram is what we're testing with.
I'm stuck. What physics principle would cause this? How can I prevent it?
Notes:
- This is a system fault, not a single-board fault. It happens on all our boards.
- I have tried re-soldering the pins. That's not the problem.
- It isn't the gain resistor R7. I've put that on long leads to test its twist separately. Twisting it doesn't make any difference.
- The resistor R7 is 220 ohms which equals an amp gain of 456
- The power supply rail, AVdd, measures steady at 3.29V
- The IC is the industry-standard AD623ARM (uSOIC package)
- For those who really must see it, here is the board — though I'm afraid that it will raise more red herrings than answers:
Best Answer
There are known effects like this that need to be taken into account for high precision circuits. Thermal gradients can also have adverse effects, component orientation across or along stress and thermal gradients etc.
Of course we have to do some guessing because we can't magically know what is in the package. But an educated guess is that the die is either eutectic bonded or glued very rigidly to the bottom of the package cavity. A small SOIC package is very non compliant (i.e. rigid) so the stresses translate directly into the package die cavity floor and then through the die attach into the Si substrate. Stress can adversely affect Si performance by affecting the electron/hole mobility and Si has known piezo resistance (through similar effects of lattice changes).
In fact Intel uses localized stress to increase the performance of PMOS transistors at some process nodes. In laying out precision circuits in silico it is recommended that sensitive amplifiers in Si not have metal layers over them so that the transistors are not adversely affected. (but here it is a matching issue).
to test the hypothesis: I recommend desoldering the amplifier, and then attaching short stubs of PTH (resistor would work) leads to lift the package up off the PCB so the stress doesn't translate into the package. Once you've fiddled with this and re-fired it up. You should see a change and therefore a verification. USe the new "legs" as compliant members. Or use solder braid if you want to get really carried away.
Solutions? a DIP version of the same part will have less of an issue because the leads are compliant. In that case using a compliant thermal compound under the package to get heat out might be used.
You should also consider your board design as a contributing factor. Perhaps running stiffeners (in the existing design) as a test will help eliminate/study the issue. I'd epoxy stiffer pieces of FR4 (on edge) just to see.