Electronic – Application of set_clock_latency

fpgatiming-analysisvlsi

I am learning about VLSI static timing analysis (STA) and some applications of SDC commands. I'm probably still missing some big picture concepts, but my question is about "why" when it comes to using set_clock_latency.

I see from the command there is an option to specify the latency from -source (the originating point of the clock such as a PLL) to the point where the clock is defined (like a port pin), and then there is a different set of options to specify network latency (from the point where the clock is defined to the final clock pin of a flop).

What's a good use for this? When do you care about the latency between the source and port pin? Wouldn't caring about timing relative to the pin be good enough? I can see the -min/-max/-early/-late being useful, but couldn't these values get rolled up into a "set_clock_uncertainty" command?

And for network latency, isn't this something the tools should worry about since it's handling the clock tree synthesis? What is gained by me directing the tools, and what value would I even put?

Best Answer

Your assumption on network latency is correct. If a tool is handling clock tree synthesis (CTS), we don't need to specify "ideal" network latency.

When do we need then?

Note that CTS is performed by a P&R (place and route) tool such as Synopsys IC Compiler. There is no clock tree in synthesis or post-synthesis STA (static timing analysis), the tools can't know actual clock latencies.

We specify ideal latencies, therefore synthesis/STA tools have more accurate input and give more accurate output. These ideal values usually come from past experience or previous P&R results.

Using the set_clock_uncertainty command for that purpose wouldn't be a good idea. Ideal network latencies are not needed in P&R (after CTS stage) or post-P&R STA, but clock uncertainty is.

If you define your clocks propagated in post-P&R STA, ideal network latencies are overridden¹ and actual values are used. This brings more flexibility.

set_propagated_clock [all_clocks]

I have never needed to specify source latency, so my answer is about network latency only.

^{1: Valid for Synopsys tools, the behaviour can be different for other EDA vendors.}

Related Solutions

Electronic – Does it always make sense to constrain an I/O port

Well, it does make sense to apply meaningful constraints if you actually care about timing and it does matter. How to constrain it heavily depends on your design. Thankfully, Altera has tons of examples for different cases.

But if you don't care at all then the best way to go is to mark that path as a false path so that Time Quest is happy and synthesizer does not hang for hours trying to route your design in order to meet timing requirements that you don't really have. That you can do with set_false_path command. For example:

set_false_path -from * -to [get_ports { output_port }]

(where output_port is a module's top level port assigned to a pin)

If Time Quest gives you a diagnostics that not every output port has a delay, you may want to add some dummy delay as well, like this:

set_output_delay -clock [get_clocks src_clk] 2 [get_ports { output_port }]

For a more practical example, you can check out this SDC file for this top-level module, the path to led_n is market as false path there since I pretty much don't care about timing from my logic to the LEDs.

Hope it helps.

Electronic – How to create a triple redundant clock tree in FPGA manually

That's a doozy of a question. What's the research for?

I know the approach I'm going to suggest won't resolve the problem with the tools complaining, but it might minimize the skew in an actual implementation. I'm not familiar with Altera FPGA's, I've worked mostly with Xilinx S3 and S6 parts; I know this approach can be made to work in an S3, but not an S6, so it might be possible in your case.

In the S3, you can make small adjustments to the phase of the managed clocks (see pg4,5); in a research paper that I've read (I'm still looking for it, will update with a link if/when I find it), the researchers used this capability and a feedback loop to fine-tune the synchronization of a comms link.

If your FPGA has similar capabilities then you might be able to do something similar: use feedback loops to synchronize your three PLL's. It might also be able to help with the problem that three external clock sources and three PLL's will never have identical frequencies. They may be close - to within a few ppm - but never identical.

Best Answer

Related Solutions

Electronic – Does it always make sense to constrain an I/O port

Electronic – How to create a triple redundant clock tree in FPGA manually

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