As part of a project, I'd like to test the correct operation of a set of SPST switch ICs (maybe 8 or 16 or so). Each device contains six independent switches, and they are controlled through an SPI bus. I plan to operate the switches at around 10 or 20 kHz. I'm thinking of using an inexpensive microcontroller (mabye an Arduino MEGA) to exercise the switches and count the number of times they're switching.
I think I could use the Arduino's 16-bit Timer/Counters, clocked externally by the switches under test, to count how many switch cycles are actually occurring. However, most MCUs have a limited number of timer/counter peripherals. The ATmega2560 in the Arduino MEGA has four 16-bit timers, for example (assuming I can use them all).
As I'm monitoring more than four switches (we could be looking at something like 50 individual switches to be monitored across 16 devices, say), I need another solution. This may be a shopping question, and I might just need the name of what I'm looking for, but are there multi-channel event counter ICs that can operate independently, with internal registers or memory to store the counts on each channel and perhaps raise an interrupt when some count is reached or they overflow? Thanks!
Best Answer
Your best bet is to use a cheap FPGA development board. Here is a list of them at Digikey, sorted by price. There are several in the $30 range.
Get one with enough I/Os to handle the number of signals that you need to count. For example, the Lattice MACHXO2 board has over 100 I/Os that go to 0.1" pin headers. It is programmable over USB and the development software is free to download.
As for programming the FPGA, instead of trying to have a large number of external clock inputs directly drive a bunch of counters, it would be best to use a fixed clock, sample the external inputs, and increment the counter when a rising edge is detected. A rising edge is detected when a 0 sample is followed by a 1 sample. The clock frequency must be at least ~4X than the input frequency and the sampled inputs should go through a couple levels of registers to avoid any metastability issues.
You can also use the FPGA logic to implement an SPI or I2C interface to read counters and status, reset the counters, etc.