Because they're wired like a NAND or NOR gate. (See this question for classical CMOS NAND/NOR gates. Here the logic is just NMOS 'pull-down', not CMOS)
To read NAND flash, every transistor is switched on in the cell except the one being read. Because it's wired like a NAND gate, where if every signal is AND'ed you get a low, if you see a low on the bit line then you know the memory cell was set.
The ones place of a single-bit addition is equivalent to the exclusive OR operation, not the OR operation. Hence XOR is used instead. Note that this is not the only way to build a half adder, you can do it without using an XOR gate, but it requires more gates.
For example, here is a half adder built with only AND, OR, and NOT gates:
You can see here that an OR gate is used to form the ones place output, but an AND gate is also necessary to turn off that output when the carry output is set.
One thing to note is that these adders are usually implemented not with several separate gates, but as one optimized unit, like this:
The construction with logic gates is just a functionally equivalent version of the actual implementation.