Electronic – Assigning x in verilog

asicsynthesissystem-verilogverilog

Assume there exists a 1 bit data output port and a 1 bit dataValid output port for a module. Is it OK to assign 1'dx to the data output when dataValid is assigned 0? Will this create synthesis issues?

EDIT: X optimizations seem to happen in both Synopsys DC and Cadence RC. Consider this code (a and b are 1-bit inputs and c is a 1-bit output).

always_comb
if ( !a && !b ) c= 0;
else if ( a && !b ) c = 1;
else if ( !a && b ) c = 1;
else c = 1'dx; // Don't care about this value.

gives an OR gate which is an optimized solution as opposed to an XOR which would have been inferred if c were set as 1'd0. This is a simple example but it seems to prove that synthesis tools do perform X optimization. Considering nasty X propagation bugs and verification troubles, are X assignments worth the saved area?

Best Answer

Never assign an X in a reachable code-path, only use X for propagating simulation unknowns. This will make life slightly easier in the long run. If you want to optimise don't care logic, do that explicitly (and pick the optimum value for the unused state). That way, you get consistent behaviour more of the time (hopefully always)

Related Solutions

Electronic – Why delays cannot be synthesized in Verilog

Synthesizing means somehow converting what you have described (in Verilog here) into real hardware.

Now in your Verilog you say that you have a 50ns delay. Ok, but now, in term of hardware, how would you convert this into actual hardware?

If you are using an FPGA, how would you actually build your 50ns delay using the available FPGA resources (LUT, Registers, Ram element, ...)? By adding additional routing delays? imagine that you specify 1s delay! Impossible without using ALL the routing capability of your chip (maybe not enough). Your design can't be fitted. Same for an ASIC. You would use 80% of the silicon surface to add a delay to ONE line.

The way is it supposed to work is that you use synchronous design and you implement the delay by yourself using counters or other techniques. But delays have to be multiples of the clock of that element.

Usually you find things such as "after 10 ns" theses are propagation delays. When doing an ideal simulation on a Verilog simulator, outputs happen exactly when the inputs change. This is not realistic and does not describe the way real hardware work. To account for that you can specify after how much time your output will be changed: using the delay declaration.

Electronic – Verilog assigning wire by iterating over array

For a mutlibit wire the reduction operator & can be used:

wire [row-1:0] ready;
wire allready = &ready;

However this will not work with unpacked arrays (multi-dimensions).

One solution is to create a loop to index the dimensions ANDing the values with the result so far. This could be achieved with some thing along the lines of:

output reg allready; 

always @* begin
  allready=1'b1;
  for (int i =0; i<col; i++) begin
    allready = allready & (&ready[i]) ;
  end 
end

Best Answer

Related Solutions

Electronic – Why delays cannot be synthesized in Verilog

Electronic – Verilog assigning wire by iterating over array

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