I recently asked a question that ended up involving answers about an automatic global reset capability that FPGAs have, and though the question got solved, I'm still quite unclear about this, and would like more information. I tried to scour the web, but wasn't able to find satisfactory answers.
1) What exactly is this global reset capability?
2) Why do FPGAs have this capability?
3) How do FPGAs infer this capability?
4) Could you provide an example of code which would have the FPGA infer the global reset, and an example using the same code where the FPGA does not infer the global reset?