Electronic – Building a byte-addressable memory

Building and using large content-addressable memories is expensive and difficult. The most common design for a CAM is to have a number of addressable memory cells that compare their contents to a matched value that is passed in, and if they match they trigger a set of associated cells to produce output on a shared bus. This means two things:

• As well as the value to output, we need memory cells for the addressable content, and additional logic to perform the comparison between that content and the value being searched for. Also, because there is no single predetermined location each value can be stored in, some mechanism of allocating space for new entries to be added is required[1]. Taken together, these make the size of a CAM much larger than the size of a traditional memory that stores the same amount of data.

• Because the units output to a shared bus, they must be arranged so that only one at a time can match. This means that before an item can be added to a CAM the CAM must first be searched to ensure that it won't conflict with existing entries. If there is a conflict, the existing entry must be deleted before the new entry can be added. If the data is required to persist indefinitely (i.e. the CAM isn't being used as a cache, as most current applications of CAMs in processors are) then this means the addressable content must always be unique -- this requirement usually means that the size of addressable content needs to be quite large, further adding to the cost of implementation.

There is also a development process reason why architectures that work like this are likely to remain rare for the foreseeable future: a large proportion of CPU development work these days is performed using FPGAs to run the processor being designed. FPGAs do not usually have the kind of shared bus arrangement that CAMs are implemented with -- to select among multiple possible source values, an FPGA uses multiplexers instead, but large trees of multiplexers are slower than such a shared bus, so large CAMs in FPGAs are not usually very fast, making developing architectures that use them particularly difficult.

For these reasons, while it is possible to use CAMs to accelerate applications that use small amounts of memory, building an entire modern general purpose computer using them for all storage seems to be unjustifiably tricky.

[1] - this can be mitigated a little by the use of set-associative CAMs, but that's only really useful for caches as it makes it more likely for conflicts to arise that require an element to be deleted from the memory when it is still needed, which is an acceptable tradeoff for a cache but not for the kind of use proposed here.

1. You have 64 memory elements, and you need them 4 wide (because 16b/4b=4). You therefore have 16 banks to switch between.

2. You have a 24-bit address space, and devices with 20 address bits. 24-20=4, and 2**4=16.