Electronic – Bypass caps under BGA: Should I isolate vias from planes

bypass-capacitordecoupling-capacitorlayoutpcbpcb-design

I'm placing bypass capacitors underneath a BGA package. In some cases the caps cannot land directly on the vias-in-pad ("VIP"), so I'll need short traces from the VIPs to the caps:

decap

In this example image, the cap is 0201 (0603 metric) and the BGA has 0.4mm spacing. The VIPs are 6-mil (0.15mm) holes filled with conductive material. In the actual design, I'll have wider connections between the VIPs and the capacitor than shown here.

However, this causes the following problem: The BGA balls are connected to the power/ground planes through the inductance of the VIPs, and then there is additional inductance (the other half of the VIPs) between the planes and the cap on the other side. My concern is that the capacitor won't actually accomplish much, since any noise will hit the planes first and will be partially isolated from the capacitor.

A possible solution is to run the VIPs through the PCB without having them contact the power planes, then to the caps, and place an additional set of VIPs (to the power planes) on the capacitor pads. But then I've really increased my loop area, which I obviously don't want to do.

Are these valid concerns? What are the best practices here?

Best Answer

The ESL for an 0201 capacitor looks like this:

enter image description here

Source: https://ds.murata.co.jp/simsurfing/mlcc.html?lcid=en-us#

The inductance for a 5mil via is about 1.546nH

enter image description here
Source: http://www.saturnpcb.com/pcb_toolkit/

So the ESL of the capacitor is being reduced significantly by the vias, however, with a BGA part we can't put the capacitor next to the part so, a capacitor is better than nothing at all. If we look at the circuit we would like to use the one on the right below, but since the BGA will get in the way we place vias on the opposite side of the board and deal with the inductance. Bigger vias have lower inductance. If there is a significant worry for noise and a way to parallel the vias, then paralleling the vias could minimize inductance.

schematic

simulate this circuit – Schematic created using CircuitLab