Electronic – Can anyone explain the point of this dual PNP/NPN set

A faster BJT will probably help once you get the fundamentals sorted out.

There are two (probably) new miracle working friends that you should meet.

• Anti saturation Schottky clamp

• Speedup capacitor.

• (1) Connect a small Schottky diode from base to collector
  (Anode to base, Cathode to collector), so that the diode is reverse biased when the transistor is off.

  When the transistor is turned on the collector cannot fall more than a Schottky "junction" drop below the base. The transistor this cannot go into saturation and charge accumulated is much smaller so is quicker to get rid of on turn off. Example of this from here

Look at the internal block diagrams for Schottky TTL. Note how this compares. This is primarily what allows Shottky TTL to be faster than standard TTL.

• (2) Connect a small capacitor in parallel with the resistor.
  This is known as a "speedup capacitor".
  Sounds good :-). Better for on than off but has a role both ways.
  It helps to "sweep charge" out of the base emitter junction capacitance on turnoff and to get charge in there on turn on. As per example below from here. This page is VERY worth looking at.

They note (more worthwhile material on page)

• Reducing storage time. The biggest overall delay is storage time.
  When a BJT is in saturation, the base region is flooded with charge carriers. When the input goes low, it takes a long time for these charge carriers to leave the region and allow the depletion layer to begin to form. The amount of time this takes is a function of three factors:

  • The physical characteristics of the device.

  • The initial value of Ic

  • The initial value of reverse bias voltage applied at the base.

• Once again, we can't do much about the first factor, but we can do something about the other two. If we can keep just below saturation, then the number of charge carriers in the base region is reduced and so is . We can also reduce by applying a high initial reverse bias to the transistor.

  Fall time. Like rise time, fall time () is a function of the physical characteristics of the transistor, and there is nothing we can do to reduce its value.

  Putting all these statements together, we see that delay and storage time can be reduced by:

  Applying a high initial value of (to decrease delay time) that settles down to some value lower than that required to saturate the transistor (to reduce storage time). Applying a high initial reverse bias (to reduce storage time) that settles down to the minimum value required to keep the transistor in cutoff (to reduce delay time). It is possible to meet all of these conditions simply by adding a single capacitor to a basic BJT switch. This capacitor, called a speed-up capacitor, is connected across the base resistor as shown in Figure 19-7. The waveforms in the figure are the result of adding the capacitor to the circuit.

  When initially goes high, the capacitor acts like a short circuit around. As a result, the input signal is coupled directly to the base for a brief instant. This results in a high initial voltage spike being applied to the base, generating a high initial value of . As the capacitor charges, decreases to the point where is held just below the saturation point.

  When the input first goes negative, the charge on the speed-up capacitor briefly drives the base to –5 V. This drives the transistor quickly into cutoff. As soon as the capacitor discharges, the base voltage returns to 0 V. This ensures that the base-emitter junction is not heavily reverse biased. In this way, all of the desired criteria for reducing switching time are met.

• (3) See how that goes. If not good enough we can see if we can add some regenerative drive next.

LSTTL & even faster friends:

Warning !!!!!!!!!!!!
Looking in here whence the below diagram came from, is liable to result in you and your soldering iron and/or breadboard staying awake all night :-).
Many good ideas.
Can you do a Miller killer ? :-).

Note that low power Schottky uses Schottky diodes whereas the earlier Schottky TTL used Schottky transistors - an apparent step backwards.

Holding the P-channel MOSFET closed (gate at 5V) will use hardly any power. It is basically the same as holding an N-channel MOSFET gate at 0V.

(See http://www.vishay.com/docs/91076/91076.pdf for a p-channel version of the IRF530 - same gate-source leakage current of +-100nA max)

To prevent powering the LED array via CLK or DAT you will need to either drive them low or set them to high-impedence when the MOSFET is off. Since CLK and DAT are both outputs, simply driving low is fine.

Note: This does not apply to your circuit here, but for inputs you can use a tristate buffer like the 74LVC1T45 or similar to prevent powering via signal pins... See FTDI (FT232RL) powers itself through RX/TX lines for the solution I used.

Edit:

Alternative solution with existing parts

Actually, you could just move the N-channel MOSFET to the low side and drive CLK and DAT to 5V when you want to turn the LEDs off and go to sleep. That would address the problem in your first idea.