Kevin asked me to write up a real answer. Here goes...
Mike's Footprint Guide
In most CAD systems, a part footprint (a.k.a. its decal) should focus on just those things that are immutable with the part. These should include, at the very least:
Copper pads for all solderable surfaces (pins, tabs, pads, balls, whatever). Even if something is not electrically connected, it should be soldered down to provide mechanical support. DFN/QFN parts are notorious for popping off the board if you only solder the edge pins and the board (or whatever it's in) is later dropped. The thermal pad, if any, must be soldered down or you won't get the needed thermal performance.
Openings in the solder mask for solderable surfaces. You should not assume that these are the same dimensions as the copper: in most cases they should be larger! This is because the solder mask is not perfectly aligned to the copper; it can be off by up to 0.1 mm (4 mils) in any direction, so your solder mask openings should be larger than the copper by this much on each edge, so that the mask won't cover the copper even if the mask is off. The better PCB shops can align solder mask to within 0.05 mm (2 mils), which allows 0.5 mm pitch parts. A piece of solder mask should never be less than 0.1 mm (4 mils) wide, since a piece that small (called a "sliver") might simply fall off. (Skipping discussion of SMD ["solder mask defined'] pads for BGAs since I doubt you're using those.)
Silk screen pattern. This should be an outline of the part to show how it is placed relative to the pads. Check with your PCB shop to see how narrow these lines can be; 0.15 mm (6 mils) is not uncommon. Silk screen tolerance is worse than solder mask's; 0.12 mm (5 mils) in any direction is common. Therefore, keep silk screen at least that far from any solderable surface. Don't expect the PCB shop to remove silkscreen from solderable areas; there's nothing more embarrassing than getting your board back with your polarity marks on the pads themselves, so they float away (solder flux usually breaks off silk screen) when soldered. Finally, if the part is polarized, place polarization marks in silk screen, but make sure these marks are visible after the part is installed. Nothing like wondering if that capacitor, diode, or IC is on right when the circuit isn't working.
Optional items:
A paste mask specifying where solder paste is to be deposited. This can be omitted if you're hand soldering. If you're using reflow to solder BGAs or DFN/QFN parts, the paste mask becomes very important and, like the solder mask, you can't assume that it's the same dimensions as the copper.
A courtyard, which is an outline around the footprint, usually on its own dedicated drafting layer. This specifies the area of the circuit board that is reserved for that part. This keeps parts from being too close together, which makes short circuits easy and cleaning difficult. Some old-school libraries draw large brackets in the silk screen to achieve this effect; I hate that, because it wastes space you could put the reference designation or polarity mark.
Assembly drawing layer. This is usually a simplified representation of the part (a box is usually fine) with the reference designation in the middle and a polarity mark somewhere, if needed. This helps you assemble the board if you can't rely on the silk screen, and can be used for reference when debugging the board.
The relevant standard is IPC-7351B, which gives extensive guidelines and equations for determining pad size based on the mechanical dimensions and tolerances of the solderable surface in order to form an optimal solder joint. For those who don't want to do the math (i.e. most all of us), they have provided a land pattern calculator that helps with almost all of this. Note, however, that it is just a calculator: you have to pay extra for the version that exports library parts, and I don't think it can export to KiCAD anyway. Personally, I'm fine with the free version; I'm responsible for the footprint anyway, so I may as well draw it and check it, and this gives me all the numbers.
(Side note: I use Mentor Graphics' PADS at work, and it has an ASCII import/export format for footprints and other library items. So I wrote up a Python library that lets me write scripts to create all my footprints. I don't know if KiCAD has an interchange format like that, or better yet built-in scripting, but it should.)
The footprint isn't the whole story, though.
Thermal Management
Sometimes a part has a thermal pad. These are tricky for hobbyists because they can't be reached with a soldering iron and need to be connected to a net such as ground. Thus solder paste and reflow (for hobbyists, a skillet can be made to work) are used. However, the pad itself might not be big enough to dissipate the heat from the part (fiberglass is an insulator, sometimes used in attics).
There are two key thermal specifications for a part, found on the datasheet: theta_JA ("thermal impedance, junction to ambient") and theta_JC ("thermal impedance, junction to case"). Both are specified in degrees Celsius per Watt (should really be Kelvins per Watt, but oh well).
Theta_JA is what the package can do all on its own. To see if it's enough, first figure out how many watts of power your chip will dissipate (can be done by various means), multiply this by theta_JA, and add it to your highest ambient temperature (45 C may be good enough for outdoors, 60 C for the guts of a PC, and even more for an automotive engine compartment). This will give you the highest junction (chip) temperature; compare this to the datasheet's junction temperature limit (usually 125 or 150 C) to see if you're under it. If not, you need a heat sink.
There are a few ways you can do a heat sink, but they all intend to solve the same equation. Remember theta_JC? That tells us how good the package is at getting heat to the case (i.e. thermal pad). It's usually far, far lower than theta_JA since it doesn't involve sending heat through the fiberglass PCB or plastic part package. However, there is another specification, theta_CA (yep, "case to ambient"), that is set by your heat sink.
Finding the theta_CA of a heat sink isn't simple, though. For discrete heat sinks (i.e. pieces of aluminum or copper), and some materials like gap pads, the datasheet will usually tell you the impedance. For copper pours, I haven't found a good calculator (anyone?), so if desperate, I'd read IPC-2152 Standard for Determining Current Carrying Capacity in Printed Board Design. It's written regarding how much current you can put through a trace given its dimensions and location in the board stackup, but could be beaten into use here by just pretending that "current" is generating heat in the copper (some resistivity of copper math should work here; any power lost in the copper is dissipated as heat) and seeing how big the "trace" (your copper pour) needs to be.
Anyway, once you have your theta_CA, you add it to theta_JC to get theta_JA and then do the math as above to see if your part will overheat. Or you can work backwards to see what the maximum theta_CA is that lets your part live.
Copper Pour Heat Sinks
This is what you're doing now: you're adding copper to the part's thermal pad to get heat away from the part. Basically, you just add copper underneath the part, overlapping the thermal pad, and extending out whatever edges of the part are open. You will be limited by the surface area available (i.e. board size and area taken by other parts). This is why it's not part of the footprint: you don't know what it needs to be until you're laying out the board, you may need to change it during layout, and you don't want to redraw the footprint for every design. Make sure the software doesn't add thermals between your copper and thermal pad; this will render your heat sink useless.
The piece of the heat sink under the part should be covered with solder mask. This is because you don't want the thermal pad's solder to wick away from it and possibly give you a weak or failed joint. Also, a lump of solder under the wrong part of the chip can lift that end off the board, making it hard for the other pins to connect.
Once you have the heat sink out from under the chip, you can either expose the metal or cover it with solder mask. Covering it will lower the theta_CA and is desired if that's all the heat sinking you will do. Then you just need to make sure there's enough copper to keep theta_CA down (this is what your part's datasheet is recommending).
Soldered-On Discrete Heat Sinks
However, if you don't have that kind of room, you can choose to expose enough of the copper to allow you to solder a discrete heat sink right to the board. This heat sink does not need to contact the part directly, since the primary thermal path is through the PCB copper. The heat sink's thicker metal and larger surface area should give it a very low theta_CA. (Also, note that the theta (impedance) contributed by the copper between the thermal pad and discrete heat sink will be much lower than theta_CA for the copper-only heat sink because it transports heat entirely by conduction, not radiation.)
Ground Plane Heat Sinks
Another technique commonly used in the industry (and recommended by some data sheets) is to put several vias in the thermal pad, all connecting to the ground plane (in a multilayer board). This way, the ground plane is your heat sink! (Note: these vias must be flooded over where they connect to the thermal pad and ground plane; if the PCB software puts thermals in there, the magic dies.) However, if these vias are not filled, the thermal pad's solder will flow down them by capillary action, away from the pad, weakening it (as described above). To avoid this, either fill the holes (expensive) or put a copper pour under the chip as above, and put all the thermal vias in the solder-masked copper (my recommendation).
Note that if the copper pour heatsink isn't grounded, we get rule errors because the copper and pad don't have the same net (they don't have a net because it would only have one "pin") and they overlap, so we add a note to the drawing telling the human to ignore those errors.
Hope this helps you keep your chips from frying!
Best Answer
No.
How would such a feature work anyway? What would be the boundaries of pour1 and pour2? You could perhaps envision a pour outline as a part of a footprint, but that is also not possible (and would still create all sorts of issues during layout).