Electronic – Can oscillations occur in VHDL with concurrent statements

fpgavhdl

Imagine we had two concurrent statements that depend on each other:

ARCHITECTURE Behavior of xxx IS
BEGIN
    s1 <= (A and B and s2);
    s2 <= (B and C and s1); 
END Behavior;

So, if A or B or s2 changes, s1 is updated. Then, since s1 updates, s2 is updated. Since s2 is updated, it would seem that s1 is updated again .. etc.

Can such things occur in VHDL? Of course in a real system, then the output would oscillate, but I have very little insight into how VHDL code gets synthesized into hardware.

Best Answer

If your VHDL description exhibits combinatorial dependency cycles, then the synthesizers will generate the exact same circuit. If you want it, you get it. However, warnings will be emitted, because it is difficult (but not impossible) to tell whether the circuit will oscillate or not (that is : will behave as pure combinatorial circuit circuits or sequential circuit). So the synthesis algorithms prefer to inform you about this danger. Such cyclic circuits also cause several difficulties in mainstream SoC design flows : for instance during timing analysis...

Please note that your question is indeed a research topic. For instance, you can read about this in several known articles :

To sum up, this resort to cyclic combinatorial circuit can be interesting when they can stabilize, because their performance (area and speed) will be better than a sequential counterpart. However, as mentioned earlier, this is not mainstream and as such still not recommended in classical (industrial) design flows.

Concerning VHDL simulation, the simulation algorithm is event-driven : an evaluation of a concurrent assignment (ou process) can lead to new evaluation of other parts or of itself. This is not a problem for the simulator. Again, depending of the circuit described, this behavior will stop (sequential behavior) or not (infinite loop).

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