Electronic – Carry look ahead adder/subtractor & Overflow, Negative Bits

addercarry-look-ahead

I am suppose to design a carry look ahead adder with …

Input flag bits

E (Enable)
S (Subtraction)

Output

The usual sum & carry out
O (Overflow)
N (Negative)
Z (Zero)

But the question is vague … It says if

E = 0, S = 1, do subtraction
E = 0, S = 0, do addition
then if E = 1? What do I do? What do usual circuits do? I suppose if 0 is enable, 1 is disable, then I put all outputs 0?
For overflow bit, I suppose the below, where \$C_{in}, C_{out}\$ are carry in/out of MSB/Sign Bit and \$S\$ is subtract bit. The 1st half checks if Cin is different from Cout (of MSB), when doing subtraction. And the 2nd half checks if theres a carry out when doing addition. Is my implementation correct?
For negative bit I also check if doing subtraction using \$S \cdot MSB\$?

Best Answer

Ask your professor if the question is vague. But your assumption that E=1 means disable is probably correct.

Related Solutions

Electronic – How to determine overflow from an adder/subtractor

From http://en.wikipedia.org/wiki/Two%27s_complement:

"The last two bits of the carry row (reading right-to-left) contain vital information: whether the calculation resulted in an arithmetic overflow, a number too large for the binary system to represent (in this case greater than 8 bits). An overflow condition exists when these last two bits are different from one another. As mentioned above, the sign of the number is encoded in the MSB of the result."

So your example, when done in 3 bits, has an overflow, because the carry into the highest bit is 1, the carry out of it is 0. (Also easy to see intuitively: you start with two positive numbers and end with a negative number). You tried to make things a bit confusing by writing the result in 4 bits, but you omitted the carry out of the 3th bit. When done in 4 bits there is no overflow, because the last two carry bits (into and out of the 4th bit) are both 0.

The correct way to note youre addition (in three bits) is:

 011
  011
+ 001 (2s)
=======
  100

Electronic – How to determine if a Carry Look Ahead Adder Overflows

I thought about seeing what my brain could regurgitate of long ago explnatins, as opposed to commin sense observations, BUT here's a page which does it all very well indeed.

They explain a "nice" 'trick'.

Two's compelment overflow detection can be achieved by XORing the carry-in and the carry-out bo=its of the leftmost full adder.

Their diagram. See above ref for detailed comment:

enter image description here

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Related Solutions

Electronic – How to determine overflow from an adder/subtractor

Electronic – How to determine if a Carry Look Ahead Adder Overflows

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