Electronic – How to determine overflow from an adder/subtractor

adder

I suppose in binary addition (no negative numbers), overflow happens when theres a carry out?

Then for subtractor (2s complement), how do I determine it? From my understanding of my lecture notes, overflow happens when theres a change in sign or carry in of MSB is different from carry out? Is that true?

Then suppose \$011_{2s}+001_{2s}=100_{2s}\$ the answer is correct, but carry into MSB is 1 but carry out is 0, so according the the rule above, its an overflow?

  11
  011
+ 001 (2s)
=======
 0100

Suppose \$X\$ & \$Y\$ are my sign bits, \$S\$ is my MSB generated and \$C_{in}, C_{out}\$ are my Carry in & out. I will implement Overflow, \$O\$ as

Suppose the above were correct, I will implement the logic to determine an overflow like
$$Overflow = (Sign 1 \odot Sign 2)(Sign 2 \oplus Carry Out) + (Carry In \oplus Carry =Out)$$

Best Answer

From http://en.wikipedia.org/wiki/Two%27s_complement:

"The last two bits of the carry row (reading right-to-left) contain vital information: whether the calculation resulted in an arithmetic overflow, a number too large for the binary system to represent (in this case greater than 8 bits). An overflow condition exists when these last two bits are different from one another. As mentioned above, the sign of the number is encoded in the MSB of the result."

So your example, when done in 3 bits, has an overflow, because the carry into the highest bit is 1, the carry out of it is 0. (Also easy to see intuitively: you start with two positive numbers and end with a negative number). You tried to make things a bit confusing by writing the result in 4 bits, but you omitted the carry out of the 3th bit. When done in 4 bits there is no overflow, because the last two carry bits (into and out of the 4th bit) are both 0.

The correct way to note youre addition (in three bits) is:

 011
  011
+ 001 (2s)
=======
  100
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