The data sheet for the CD4013 specifies a "setup time" value, but when you look at the included waveforms, that value describes the timing between the "data" input and the leading clock edge.
What specification do I use to determine the minimum time from a SET
or RESET falling edge til the leading clock edge?
There must be enough "daylight" between the falling edge of the SET or
RESET input and the clock's rising edge so that these two inputs won't
override the clocks ability to "latch" the data on the input.
I like to know how much time is needed between the deactivation of SET or RESET and the first active clock edge to safely latch the data. The t(SETUP) in the data sheet is only shown in the waveforms as the time between the center of the leading edge of the DATA input (either rising or falling) and the center of the rising edge of the clock. At a 5MHz clock (100nSec high, 100nSec low), I need to ensure that the reset signal has "completely" disappeared before the clock leading edge arrives.
Best Answer
The set and reset are asynchronous. They are not affected by the clock, so they do not have a setup time spec. Most 4013 datasheets have some kind of internal logic diagram.
In a master-slave flipflop commonly used in a D latch, the rising edge of the clock input disables changes in the master ff and enables the slave ff to latch the output state of the master ff. The Set and Reset inputs go directly to the slave ff as extra inputs, bypassing the master-slave relationship and its dependence on a setup time.