# Electronic – Choosing the right voltage divider by load

androidresistorsvoltage divider

I'm using an Android IOIO board to detect simple digital pulses from a 12v source.

The input pins are 5V tolerant. Would a simple voltage divider work in this situation? I guess my concern is whether or not the IOIO would have much if any load pull when used as a digital input sensor.

I would say and I don't know this for sure that the max load would be 20mA??

What considerations do I need to make in selecting the correct resistor value ratio to go from 12v to 5v?

I also have these resistors available:

0Ω, 1.5Ω, 4.7Ω, 10Ω, 47Ω
100Ω, 220Ω, 330Ω, 470Ω, 680Ω
1kΩ, 2.2kΩ, 3.3kΩ, 4.7kΩ, 10kΩ
22kΩ, 47kΩ, 100kΩ, 330kΩ, 1MΩ

I've calculated that I can get 3.84V by using a 10k and a 4.7k. Will this be too much resistance?

A digital pin, when used as input, offers very little input resistance. Note that this holds for DC current.

Since you want to scale \$12V\$ to be \$5V\$: $$5V=12V\frac{R_1}{R_1+R_2}$$ that leads to \$R_1=0.417(R_1+R_2)\$. There still is a degree of freedom, that is the total divider resistance. The factors that can help you to choose it are:

1. Your \$12V\$ output resistance
2. Your Android board input resistance
3. The speed of your pulses

Please note that the third factor might be the dominating one. A good cmos circuit has an input impedance composed by the parallel of a resistor and a capacitor, the resistor being some \$10^{12}\Omega\$ while the cap being in the \$10\text{pF}\$ ballpark. That means that you can forget about factor 2. A good digital circuit can usually deliver \$1\text{mA}\$ at least, maybe reaching \$10\text{mA}\$ in most cases. Moreover your driver circuit works at \$12\$V, that's probably quite stiff. Factor 1 should not be a concern too then, unless you are going to use very low resistors for the divider.

Now to factor three. The cmos input capacitance sees a resistance that is the parallel between the divider resistors\$^1\$, i.e. $$R_P=\frac{R_1R_2}{R_1+R_2}$$ As you might know this whole circuit behaves like a low pass filter, its dominant pole being \$f_p=(R_PC_{in})^{-1}\$, where \$C_{in}\$ is the cmos input capacitance. Now, you wanna keep that pole quite higher than the higher frequency you want to read on the board.

Assuming your highest frequency is \$1\text{MHz}\$ you need \$f_p\gg10^6\text{Hz}\$ that leads to \$R_P\ll(10^6\cdot C_{in})^{-1}=100\text{k}\Omega\$. Let's choose \$R_P\approx10\text{k}\Omega\$, and since the two resistors will be of the same order of magnitude \$R_P\approx0.5(R_1+R_2)\to R_1+R_2 \approx 20\text{k}\Omega\$.

Finally: $$R_1\approx 8.3\text{k}\Omega$$ $$R_2\approx 12\text{k}\Omega$$

Now you need to choose between your resistors, that are quite limited actually. Depending on your signal bandwidth you can safely increase the values somewhat, just keep the 2:3 ratio. 22k and 33k would be just perfect, if you are ok with the filtering involved. If you want fast signals go with 2k2 and 3k3 and call it a day.

\$^1\$ Actually you should sum the \$12\$V device output resistance \$R_o\$ to \$R_2\$ but I am assuming that \$R_o\ll R_2\to R_2+R_o\approx R_2\$.