Electronic – Circuit Diagrams – 2 Input/Output Current Source

Although I haven't labeled them, there are 5 interesting nodes in the network.

As drawn, your circuit contains only 2 nodes. The entire outside ring is connected by perfect wires, and so it's just one node from the point of view of circuit analysis.

Does any one have an idea on how I would go about designing the current controlled source in PSpice?

PSpice provides an "F" Element which is in itself a current-controlled current source. Simply place one of these in your circuit. The CCCS element will have a source port and a sense port.

You simply place the element so that the source port is where you show the CCCS in the hand drawing. Then connect the sense branch so that the controlling current flows through it. Normally this means breaking a wire in the hand drawing.

However, in this circuit you will have a problem because both terminals of the sense port are connected to the same node. Probably PSpice will refuse to simulate this circuit; but even if it does, the results are ambigous. In terms of your drawing, there's no reason for current from the bottom end of the V source to go by the "i1" path vs going the other way around through the yellow, purple, and red arrows.

Also, you will also have to designate one of your two circuit nodes as ground before running a simulation.

First, \$v_{in}\$ is an AC signal voltage while \$V_{GS}\$ is a DC bias voltage. These are treated separately.

From a small-signal perspective, the current source (lower FET) is effectively an open circuit so there is effectively no voltage division for the AC signal. This is why \$v_{in}\$ appears at the output node unattenuated (assuming the output node is connected to an effectively open circuit).

From a DC bias perspective, the gate of the top FET is at (presumably) zero volts so the source, which must be more positive than the gate, must be at 2.8V (using the values in the book and assuming the FETs are identical).

However, note that this is not \$V_{GS}\$ since, in fact, \$V_{GS}\$ for both FETs is -2.8V. In other words, the voltage at the source of the top FET is $$v_{in} - V_{GS}$$