Electronic – Clock signal purpose

1. Is there any documentation for that is generic or covers Spartan-6 LX9 board?

   The DCM is fully contained within the FPGA chip. So it doesn't matter what board you have. The documentation will be based on what chip you have.

   For the Spartan-6 family, see the Spartan 6 Clocking Resources User Guide

2. Is using this module is absolutely necessary in this example? Is that possible to do the same thing easily w/o using that module?

   If you're just blinking LEDs, you probably don't need to use the DCM. Probably they used it because its a very complicated block and they specifically wanted to provide an example of using the DCM without much else in the way of complex logic to confuse things.

3. How people usually go about vendor specific things like clock? For example, if one wants to target both Altera FPGAs and Xilinx ones. What is the process to achieve that? Is it similar to ordinary C pre-processor typedefs etc?

   Unfortunately, complex hard cores like clock management is one of the areas where there's not much compatibility between vendors. You'll likely have to make significant code changes if you want a design using these features that is portable between two device families, whether they're from the same or different vendors.

   If you can simplify your interface so that you just have one input clock coming from off-chip, and a number of derived clocks that are distributed to the rest of your logic, the cleanest solution is probably to push all of the vendor-specific code into a single module that you can instantiate in your top-level code. Then you can just use a different "clock management" module depending which device you're targeting.

   If you want to do something like dynamically changing the phase relationship between various clocks, or switch between several choices of reference clock frequency, you probably have no choice but to re-code substantial chunks of logic for different target devices.

   Remember that in addition to the Verilog code, there will probably also be numerous constraints that need to be defined, and these will also need to be different for different devices.

First of all, throw out this concept of 'instructions'. They do not exist in Verilog. Nothing is executed. Verilog, VHDL, SystemVerilog, etc. are what are called hardware description languages. They are not executed. They are not interpreted. They define hardware components (logic gates, flip flops, registers, etc.) and their interconnections. (Not entirely accurate I suppose; but the only verilog that you can put on an FPGA - synthesizable verilog - will not be executed or interpreted. Testbenches are a different animal.)

Clocks are used to drive flip flops and registers. Data can be shifted into flip flops and registers on the edges of the clock. So inside of an always @(posedge clk) block, all of the statements will be 'executed' simultaneously and the results will be latched into the registers on the clock edge, according to the rules of how the HDL statements are interpreted. Be very careful where you are using = and <=, though. The meaning of these two assignment operations is very different inside of an always block. The basic idea is that all of the = operations are dealt with first in order of appearance. This happens at the propagation speed of the gates. Then all of the <= are dealt with at the same time, storing the argument into a register. The only thing the clock affects in this case is precisely when the registers are updated. If you are running a simulation, it won't matter how many operations need to occur between registers, but on an FPGA the clock will have to be slow enough to ensure that any changes have been able to propagate through the logic.

Faster clocks can be generated using a device called a phased lock loop (PLL). PLLs are not synthesizeable in verilog, but generally there is a way to instantiate a dedicated PLL component on the FPGA you are using. Actually, I take that back, you can certainly make a digital PLL in verilog, but you can only use it to generate signals lower than the clock frequency. A PLL contains a voltage controlled oscillator, one or more frequency dividers, a phase comparator, and some control circuitry. The output of the VCO is divided down and phase compared with the input frequency. The VCO control voltage is adjusted until the divided down VCO output precisely matches the frequency and phase of the reference signal. If you set the divider to 5 and use 50 MHz for the reference frequency, the PLL will generate a 250 MHz signal that is precisely phase locked to the 50 MHz reference. There are several reasons for doing this. Using a PLL allows generation of multiple clocks so different logic can be run at different speeds e.g. for specific peripheral interfaces or for slow, complex combinatorial logic. It also can allow the device to control its own clock frequency to save power.

Blocking statements inside of always blocks will generate combinatorial logic. Again, this logic will generally always be 'executed' regarless of the clock because it defines actual logic gates. It can be beneficial to use a few temporary variables, but care must be taken to ensure that there isn't so much extra logic that the timing requirements are not met.