cmoslogic-gates
What happens to Voh and Ioh when the number of loads connected to the output of this logic gate increases?
My interpretation is: the increase in number of loads decreases the equivalent impedance, which causes the current Ioh to increase. Is this view correct? But I can't visualize what happens to Voh.
simulate this circuit – Schematic created using CircuitLab
Imagine a load resistor (say 10K) from output to Vdd, and make X_1 and X_2 low. Ideally, output should be 0.0V. You can figure out what it is (not 0V).
Now imagine a 10K load resistor from output to GND and make X_1 low and X_2 high. Ideally, output should be Vdd. You can figure out what it is (not Vdd).
simulate this circuit – Schematic created using CircuitLab
The two leftmost transistors forms a simple not gate, but it is powered only when \$V_{x1}\$ is high. Luckily enough the passgate on the right is turned on when \$V_{x1}\$ is low instead, and directly connects the \$V_{x2}\$ input to the output.
To sum it up:
in a table:
x1 x2 out
0 0 0
0 1 1
1 0 1
1 1 0
that's a xor gate.
Best Answer
Inside the inverter there is a switch, this switch flips between Voh and Vol. Now, this switch has resistance (like pretty much everything) and so when you pull more current, the switch isn't able to pull the output as close to Vcc or GND as it would have been able to other wise. Basically, Voh drops and Vol rises (assuming equal loads in both directions)