In the image above, why does current flow backwards toward the left GND but not toward the right ?
CMOS – Understanding CMOS Timing Specifications
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As long as it's under the logic low threshold for the end-device, what's the problem? And yes, the low-side Rds_on resistance is most likely causing the discrepancy. The guaranteed "low" for a digital system (for the 1.8-5V systems i've worked on) is usually 0.5V-0.7V or less. So if your 50MHz signal goes from 0.2V to 3.1V for example, that will still operate fine. The loss of full rail-to-rail output can be from the output driver design.
Second question how do they do slew rate control in a cmos I/O buffer is there a short burst of current from a one shot or something like that?
This switching current required to do a fast on/off on the output usually comes from the bypass capacitors - making them extremely important where there is a lot of digital switching coming from an IC. Without them, you can get poor performance or even brown-outs of the IC, because the IO drivers are basically shorting VCC to the output to get the line high, and then grounding through another CMOS device to get the output line to go to GND. Current is sourced through the resistance of the FET driver stage, plus whatever internal resistors have been placed between the FET and VCC (for protection of the device, but this is up to the IC designers).
There are two issues here. First of all, many truth tables can be achieved via multiple combinations of logic functions. Consider the function not ((A and B) or (B and C) or (A and C)). That function will be true and false in the same cases as not ((A or B) and (B or C) and (A or C)), but the former includes a three-term and and the latter includes a three-term or. Consequently, one form may be more efficiently used when evaluating the high-side network and the other may be more efficiently used when evaluating the low-side network. As an interesting side note, the two functions are duals of each other, but their equivalence makes each function also the dual of itself.
The other issue at work here is that many circuits can be simplified if one moves "inverting bubbles" from outputs to inputs. Circuitry for any non-trivial function whose input is true when all of the inputs is true, or false when all of all of the inputs are false will require at least two logic stages unless it is allowed to feed current from the input and output [a "function" which always outputs high or always outputs low would, of course, not need any logic stages]. Consequently, it may be often easier to compute the inverse of a desired function than the function itself. If whatever is going to use the output of the function could be designed just as well to use accept either the inverted or non-inverted form, making the downstream stage accept the cheaper form may save cost.
It may be more helpful to look not at a single bit adder, but instead at a two-bit adder. If the carry generator for a single bit needs to accept an active-high carry in and needs to generate an active-high carry out, there will need to be two logic stages between the carry in and carry out. If the function can accepts an active-high carry in and produce an active-low carry out, however, it can be realized in one stage. Having the function produce an active-low carry out will require modifying the next stage, however. The trick is to realize that (1) if all the data inputs and outputs of the next stage are inverted, then it will naturally accept an active-low carry in, and can cheaply produce an active-high carry out; (2) in many cases, ALU inputs and outputs will come from or be sent to latching circuits; (3) in many cases, latching circuits can provide both inverted and non-inverted outputs at essentially no extra charge, which implies that they can accept inverted or non-inverted inputs at no extra charge.
Essentially what happens is that rather than needing to have each stage include an inverters so that its inputs and outputs have the same logic polarity, inversions get shifted around so that the inputs and outputs associated with alternate bits have reversed polarity. If one needed to have an ALU with non-inverted inputs and outputs, the need to add inverters to some inputs and outputs would counteract the savings realized earlier (though eliminating an inversion stage from the carry chain would still reduce propagation delays). The fact that adders are used in many contexts where inversions are available "for free", however, allows those inverters to be eliminated entirely.
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The arrow shows the current flowing through the channel of the nMOS element of the left gate, as that transistor turns on due to a rising Vin voltage, as the Cw distributed capacitance discharges.
On the right, Cw is connected to the gate of the MOSFETs, which are insulated from the channels. There is no path for current to flow to ground through the right, aside from a very small transient associated with the gate capacitance of those MOSFETs. A more comprehensive model could show a small current charging those gate capacitances, but the majority of the stored charge in Cw is moved via the channels of the MOSFETs on the left.