In a cmos driver what controls the amount of current it can source or sink? Is it the combined RDS on of the internal FETs? When you try to pull a line low I guess there's voltage stored in the capacitance of the trace and the current from that flows through the bottom FET and it's on resistance to gnd?
Second question how do they do slew rate control in a cmos I/O buffer is there a short burst of current from a one shot or something like that?
I have a clock coming out of an FPGA at 50Mhz, and for some reason it doesn't get to GND, maybe a few hundred mV above it. It does flatten out though. So I was thinking maybe it doesn't have enough pull to get it down to GND before the start of the next cycle. That made me wonder how a real CMOS I/O pad actually works.
I should add the trace is very long maybe about a foot, but impedance controlled to 50Ohm.
Best Answer
As long as it's under the logic low threshold for the end-device, what's the problem? And yes, the low-side Rds_on resistance is most likely causing the discrepancy. The guaranteed "low" for a digital system (for the 1.8-5V systems i've worked on) is usually 0.5V-0.7V or less. So if your 50MHz signal goes from 0.2V to 3.1V for example, that will still operate fine. The loss of full rail-to-rail output can be from the output driver design.
This switching current required to do a fast on/off on the output usually comes from the bypass capacitors - making them extremely important where there is a lot of digital switching coming from an IC. Without them, you can get poor performance or even brown-outs of the IC, because the IO drivers are basically shorting VCC to the output to get the line high, and then grounding through another CMOS device to get the output line to go to GND. Current is sourced through the resistance of the FET driver stage, plus whatever internal resistors have been placed between the FET and VCC (for protection of the device, but this is up to the IC designers).