Electronic – Component Not Found VHDL XILINX ISE

vhdlxilinx

i know this might be a very simple question .
i have to simulate some delays for various adders in ISE Suite . ( i'm a little familiar with vhdl concepts but ISE Environment , not at all ! )

this is the vhdl Code for Carry select adder : 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.all ; 

library UNISIM;
use UNISIM.VComponents.all;

entity csa is
  generic (
    WIDTH : natural := 32 -- adder will add WIDTH bits, should be a power of 2
  );
-- some port mappings .. 
end csa;

architecture csa_arch of csa is

  component csa is
    generic (
      WIDTH : natural
    );
    port (
      op_1  : in std_logic_vector(WIDTH-1 downto 0);
      op_2  : in std_logic_vector(WIDTH-1 downto 0);
      c_in  : in std_logic;
      sum   : out std_logic_vector(WIDTH-1 downto 0);
      c_out : out std_logic
    );
  end component;

  signal sum_loc_0   : std_logic_vector(WIDTH-1 downto 0);
  signal sum_loc_1   : std_logic_vector(WIDTH-1 downto 0);
  signal c_out_loc_0 : std_logic_vector(1 downto 0);
  signal c_out_loc_1 : std_logic_vector(1 downto 0);
begin

  base_case : if (WIDTH = 1) generate
   full_adder_0 : full_adder -- GENERATES ERROR -- 
      port map (
        op_1  => op_1(0),
        op_2  => op_2(0),
        c_in  => '0',
        sum   => sum_loc_0(0),
        c_out => c_out_loc_0(1)
      );
  end generate;

and the line creating a component of the full adder entity rises tthe error : 

Line 44: full_adder is not a component

the full adder is defined in a seprate file : ( in teh same project as another vhdl module ) 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work ;

library UNISIM;
use UNISIM.VComponents.all;

entity full_adder is
port (
    op_1  : in std_logic;
    op_2  : in std_logic;
    c_in  : in std_logic;
    sum   : out std_logic;
    c_out : out std_logic
);
end full_adder;

architecture full_adder_arch of full_adder is

begin

    sum   <= op_1 xor op_2 xor c_in;
    c_out <= (op_1 and c_in) or (op_2 and c_in) or (op_1 and op_2);

end full_adder_arch;

Best Answer

There are three ways to instantiate components in VHDL, through the use of direct entity instantiation, instantiating a declared component and instantiating a configuration of an entity.

The first two of these are shown below:

library ieee;
use ieee.std_logic_1164.all;
-- use IEEE.NUMERIC_STD.ALL;
-- library work ;
--
-- library UNISIM;
-- use UNISIM.VComponents.all;

entity full_adder is
    port (
        op_1:   in  std_logic;
        op_2:   in  std_logic;
        c_in:   in  std_logic;
        sum:    out std_logic;
        c_out:  out std_logic
    );
end full_adder;

architecture full_adder_arch of full_adder is

begin

    sum   <= op_1 xor op_2 xor c_in;
    c_out <= (op_1 and c_in) or (op_2 and c_in) or (op_1 and op_2);

end full_adder_arch;

library ieee;
use ieee.std_logic_1164.all;
-- use IEEE.NUMERIC_STD.ALL;
-- use work.all ; 

-- library UNISIM;
-- use UNISIM.VComponents.all;

entity csa is
    generic (
        WIDTH:  natural := 32 -- adder will add WIDTH bits, should be a power of 2
    );
    port (
        op_1:   in  std_logic_vector(WIDTH-1 downto 0);
        op_2:   in  std_logic_vector(WIDTH-1 downto 0);
        c_in:   in  std_logic;
        sum:    out std_logic_vector(WIDTH-1 downto 0);
        c_out:  out std_logic
    );
end entity csa;

architecture component_instantiation of csa is

    -- component csa is
    --     generic (
    --         WIDTH:  natural
    --     );
    --     port (
    --         op_1:   in  std_logic_vector(WIDTH-1 downto 0);
    --         op_2:   in  std_logic_vector(WIDTH-1 downto 0);
    --         c_in:   in  std_logic;
    --         sum:    out std_logic_vector(WIDTH-1 downto 0);
    --         c_out:  out std_logic
    --     );
    -- end component;

    component full_adder is
        port (
        op_1:   in  std_logic;
        op_2:   in  std_logic;
        c_in:   in  std_logic;
        sum:    out std_logic;
        c_out:  out std_logic
        );
    end component;

    signal sum_loc_0:    std_logic_vector(WIDTH-1 downto 0);
    signal sum_loc_1:    std_logic_vector(WIDTH-1 downto 0);
    signal c_out_loc_0:  std_logic_vector(1 downto 0);
    signal c_out_loc_1:  std_logic_vector(1 downto 0);
begin

base_case: 
    if (WIDTH = 1) generate
full_adder_0: 
        full_adder -- GENERATES ERROR -- 
            port map (
                op_1  => op_1(0),
                op_2  => op_2(0),
                c_in  => '0',
                sum   => sum_loc_0(0),
                c_out => c_out_loc_0(1)
            );
    end generate;
end architecture;

architecture direct_entity_instantiation of csa is

    -- component csa is
    --     generic (
    --         WIDTH:  natural
    --     );
    --     port (
    --         op_1:   in  std_logic_vector(WIDTH-1 downto 0);
    --         op_2:   in  std_logic_vector(WIDTH-1 downto 0);
    --         c_in:   in  std_logic;
    --         sum:    out std_logic_vector(WIDTH-1 downto 0);
    --         c_out:  out std_logic
    --     );
    -- end component;   

    signal sum_loc_0:    std_logic_vector(WIDTH-1 downto 0);
    signal sum_loc_1:    std_logic_vector(WIDTH-1 downto 0);
    signal c_out_loc_0:  std_logic_vector(1 downto 0);
    signal c_out_loc_1:  std_logic_vector(1 downto 0);
begin

base_case: 
    if (WIDTH = 1) generate
full_adder_0: 
        entity work.full_adder -- GENERATES ERROR -- 
            port map (
                op_1  => op_1(0),
                op_2  => op_2(0),
                c_in  => '0',
                sum   => sum_loc_0(0),
                c_out => c_out_loc_0(1)
            );
    end generate;
end architecture;

The entity and architecture for full_adder is included for the second csa architecture (direct_entity_instantiation).

Note that there is an implied library declaration for the library simple name work in VHDL. A use clause specifying use work.all; would make all the declarations for primary units in the current working library available. The architecture direct_entity_instantiation could have taken advantage of that and not used a selected name to specify full_adder in the generate statement.

I analyzed both architectures, and verified they work with the generic WIDTH set to 1. Elaborating and running tells us there's no connectivity issues for width 1.

A component instantiation with a component declaration does not require the full_adder to analyze, but does require it be analyzed before csa for elaboration.

Likewise the direct entity instantiation requires full_adder be found in the working library to analyze csa successfully.

See IEEE Std 1076-2008 11.7 Component instantiation statements.

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