Electronic – connecting logic gates

The problem here is that you're misunderstanding (or not having the basic understanding) of how MOSFETs work, in particular the \$V_{GS}\$.

On an N-channel MOSFET the gate voltage has to rise a certain amount above the source pin. On a P-channel it has to fall a certain amount below the source pin.

In your schematic the N-channel's source is connected to \$V_{CC}\$ and the P-channel's to GND. If the threshold is, say, 1.2V (a reasonable logic level threshold), then the input logic HIGH would have to be at least 1.2V above \$V_{CC}\$ and the logic LOW would have to be below -1.2V.

That, as you can see, just isn't practical.

CMOS parts like the 4011 have a very high input impedance and will have a random value if left unconnected.

If you are connecting your switches between an input pin and the positive supply, you need a pull-down resistor (10K or so will do) to ensure that the input will be low when the switch is open. If your switches are between the input pin and ground, use a pull-up to the positive supply to make the inputs High when the switch is open.

Also, any unused inputs must be connected to either the positive supply or ground to ensure they don't sit at a "maybe" state and cause the input circuit of the gate to draw excessive current.

You don't need any resistors between the gates.

As one comment says, it is good practice to have 0.1 uF bypass capacitors between the power supply and ground at each IC - more important with flip-flops and other clocked logic than with simple gates, but it is good to get in the habit...

^{simulate this circuit – Schematic created using CircuitLab}