Electronic – Constraining a 7 segment display in VHDL

Actually your first guess is not as afar off as some are claiming.

A CPU is built around something called an "Arithmetic Logic Unit" (ALU) and a simplistic implementation of that is to have the logic gates implementing all basic operations wired up to the inputs in parallel. All of the possible elementary computations are thus performed in parallel, with the output of the actually desired one selected by a multiplexor.

In an extremely simple (chalk-board-model) CPU, a few bits of the currently executing instruction opcode are wired to that multiplexor to tell it which logic function result to use. (The other, undesired results are simply wasted)

The actual technology used to implement the computations in the ALU varies - it could be "real" logic gates, or it could be LUT's if the CPU is implemented inside an LUT-based FPGA (one very good way to understand the essentials of stored-program computing is to design a simple processor and build it in a logic simulator and perhaps then an FPGA).

Firstly I'm assuming the signal clk is a nice clean clock signal driven from outside the FPGA, maybe by crystal oscillator, LVDS clock source or similar, preferably on a dedicated clock pin?

Your code creates a roll-over counter stored in count_time that overflows to zero after 22-bits, where cycle with all-1's sets signal check high for one cycle. So far all fine.

always @ (posedge clk or posedge rst) begin
    if (rst) begin
      count_time <=0;
      check <=0;
    end else begin
      count_time <= count_time+1;
      check      <= &count_time;
    end
end

The problem is how you use the signal check. You have added it to the sensitivity list of the process //counting on last two SSDs. Since this signal is the output from a flip flop, rather than a nice clean external clock signal, the tools are warning you. This arrangement (logic from one stage feeding the CLOCK of a subsequent register) is called a "gated clock". It is popular in ASIC design but not good synchronous design practice for targeting FPGAs.

The way to solve this is to re-write your code so that all processes are sensitive only to the clk and rst signals. The signal check will be promoted to become the CLOCK ENABLE input for all the logic within the process, I'll do one to get you started:

//counting on last two SSDs

always @ (posedge clk or posedge rst) begin
    if (rst) begin
      third <= 0;
      fourth <= 0;
    end else if (check) begin
        if (fourth==9) begin
           fourth<=0;
           if (third==1) begin
              third <= 0;
              carry <= 1;
           end else begin
              third <= third + 1;
              carry <= 0;
           end
        end else begin
          fourth <= fourth+1;
        end
    end
end

This probably isn't why the design doesn't work, but it should clear up those warnings and put you on the right path. It would be advisable to get this running in a simulator like Icarus Verilog to see if the design has any fundamental problems.

You also should:

• register the output of a,b,c,d,e,f,g,dot and anodes an so they reveal to the outside world on a common clock edge, rather than after arbitary logic/routing delays. The reg will be absorved into the pin I/O pads so don't worry about 'extra' logic usage, you'll have it anyway

• Depending on what the source (clk) clock rate is, you might want to massively reduce the base frequency of the multiplexed outputs (using enables again) - it won't work effectively if the active time for each display is just hundreds of nanoseconds before switching. To get flicker free visual aliasing aim for a redraw of about 25-50Hz on each digit, so with four displays you want to switch the output at 200-500hz. I would add many more bits to counter and use the upper bits to drive the multiplexer.