Electronic – constraint error and illegal load problem in Virtex-2

constraintsfpga

I am trying to test a very simple deskew circuit on a virtex-2pro FPGA (xc2vp30-fg676-5). I use xilinx ISE and the deskew IP (two DCMs with a DDR flop) provided by core generator. I also try to observe the related signals on GPIO pins. But I have got the following translate error in my design. The details of the error and the design is pasted below. Please give me some hints.

Resolving constraint associations...
Checking Constraint Associations...
ERROR:ConstraintSystem:59 - Constraint <INST "rex_clk"  LOC="N3" |>
   [xc2vp30.ucf(14)]: INST "rex_clk" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:59 - Constraint <IOSTANDARD="LVCMOS33" ;>
   [xc2vp30.ucf(14)]: INST "rex_clk" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

Done...
Checking Partitions ...

Checking expanded design ...
ERROR:NgdBuild:809 - output pad net 'clk_o' has an illegal load:
     pin C on block cnt_0 with type FDC

Verilog module

module xc2vp30(
    //probing
    output rex_clk,
    output rex_rst,
    output rex_cnt_i,
    output rex_cnt_o,

    input rst,
    input clk,
    output clk_o,
    output rst_o,

    input cnt_i,
    output cnt_o
);

wire clk_ddr;
reg cnt;

assign rex_clk = clk_ddr;
assign rex_rst = rst;
assign rex_cnt_o = cnt;
assign rex_cnt_i = cnt_i;

assign clk_o = clk_ddr;
assign rst_o = rst;
assign cnt_o = cnt;


always @(posedge clk_ddr or posedge rst) begin
    if(rst)
        cnt <= 1'b0;
    else
        cnt <= cnt + 1'b1;
end

////////////////////Deskew/////////////////////

deskew deskew_0(
    .U1_CE_IN(1'b0),
        .U1_CLKFB_IN(clk_ddr),
        .U1_CLKIN_IN(clk),
        .U1_CLR_IN(rst),    //high reset
        .U1_PRE_IN(1'b0),
        .U1_RST_IN(rst),    //high reset
        .U2_RST_IN(rst),
        .DDR_CLK0_OUT(clk_ddr),
        .U1_CLKIN_IBUFG_OUT(),
        .U1_CLK0_OUT(),
        .U1_CLK180_OUT(),
        .U1_LOCKED_OUT(),
        .U2_CLK0_OUT(),
        .U2_LOCKED_OUT()
);
endmodule

UCF file

NET "clk" PERIOD = 40 ns HIGH 50%;
NET "clk" TNM_NET = clk;
#================================================ Pin assignment
#------------------------------------------------ Clock, reset, LED, and SW.
INST "clk"          LOC="B13" | IOSTANDARD="LVCMOS33";           # Clock input (X2)
INST "rst"             LOC="E21" | IOSTANDARD="LVCMOS33";           # Reset input

INST "clk_o"       LOC="AE1" | IOSTANDARD="LVCMOS33";              # Clock output
INST "rst_o"          LOC="Y26" | IOSTANDARD="LVCMOS33";               # Reset output
INST "cnt_o"          LOC="U2" | IOSTANDARD="LVCMOS33" | DRIVE=6;  # data output
INST "cnt_i"          LOC="V5" | IOSTANDARD="LVCMOS33" | DRIVE=6;  # data input

INST "rex_clk"     LOC="N3" | IOSTANDARD="LVCMOS33" ;           #  observe clk output
INST "rex_rst"     LOC="M4" | IOSTANDARD="LVCMOS33"| DRIVE=6; # observe Reset output

INST "rex_cnt_i"     LOC="L3" | IOSTANDARD="LVCMOS33"| DRIVE=6; # observe
INST "rex_cnt_o"     LOC="K3" | IOSTANDARD="LVCMOS33"| DRIVE=6; # observe

Best Answer

That Verilog module is top-level, right? Make sure, because the toolchain will try to map the UCF onto the top level module. If you're using a third-party toolchain that "sits above" the Xilinx toolchain, you will want to investigate what top-level file the third-party toolchain is creating.

I looked in my UCF files and I don't see INST at all. I use NET everywhere (with the exception of one TIMESPEC on the main clock)

Another thing I noticed...

always @(posedge clk_ddr or posedge rst) begin
    if(rst)
        cnt <= 1'b0;

You are using posedge on two different signals. Pin C on FDC probably means the "clear" pin of a D Flip Flop (hence, FDC). You probably actually want an FDCE (D Flip Flop with async Clear and clock-Enable), or an FDE (D Flip Flop with clock-Enable). The synther is probably confused because flip flops only have one edge-sensitive input and you're asking it for a flip flop with two edge sensitive inputs.

Did you want an async clear, or a sync clear? If async, get rid of the "posedge" in front of rst. If sync, get rid of the entire "posedge rst". Async clear (FDCE) is trouble unless you know what you're doing; go for the sync clear (FDE).

Related Solutions

Electronic – Help needed with SPARTAN-3AN FPGA frequency doubler

Basically what it is saying is that there is a fast path (a direct connection) from certain pins into the DCM but for some reason this fast path can't be used. This could be for a number of reasons. If I'm reading the datasheet right, P53 isn't a clock capable pin so there won't be a fast path. You can also get problems if you've LOC'd the DCM to the wrong site in the UCF or you are using many DCMs such that the ideal site isn't available. Looking at your project though, it looks like this is the only thing in the design?

Where did you get the PAD53 constraint for the input clock?

Electronic – cannot fix: warning signal clk IBUF has no load please help!

Some hints for and questions to your code:

signal nextColor should not have a default value, because it's not mapped to a register
signal nextColor : color_type;
signal qtemp misses a default value: it's a counter/mapped to a register
secondly, this signal represents a counter and it's used in arithmetic calculations. So qtemp should be of type (un)signed or integer/natural. Doing artithmetic calculations on std_logic_vector is not a recommended style.
signal qtemp : unsigned(24 downto 0) := (others => '0');
qtemp should also be reset to 0 after 1 second passed by (as David Koontz wrote in the comment below)
if you change the type of qtemp you can rewrite the test (qtemp = "10111110101111000010000000") to (qtemp = 50000000)
Actually, it should be 49,999,999, because your counter starts at 0.
ONEsec_flag is asynchronous set and synchronous reset -> try to write full synchronous design.
line if (BaseBeat'event and BaseBeat = '1') and (ONEsec_flag='1') then can and will cause several problems:
1. BaseBeat is no clock signal, but you are using this signal as a clock. A better solution would be to use BaseBeat as an (clock)enable signal.
2. writing a rising edge condition and a clock enable in one line is no good style. Additionally it can cause synthesis tools to infer wrong hardware.
3. In combination with your else-statement this code will not be synthesizable. Here is a solution:
  
  calculating the flag (concurrent statement):
  ONEsec_flag <= '1' when (qtemp = 49999999) else '0'; -- ternary operator like ?: in C
  
  transition process:
```
transition: process(clk)
begin
  if rising_edge(clk) then         -- synchronous design using the main clock    
    if (BaseBeat = '1') then       -- using BaseBeat as an clock enable
      if (ONEsec_flag='1') then    -- using flag as an write enable (second ce)
        current_color <= next_color;
      end if;
    end if;
  end if;
end process;
```

So now, flag is calculated concurrently, it can be used to reset the second timer, otherwise a 25 bit vector will overflow after 2^25 cycles, that are 33554432:

process(clk)
begin
  if (clk'event and clk='1') then
    if (ONEsec_flag = '1') then      -- synchronous reset if one second is reached
      qtemp <= (others => '0');
    else
      qtemp <= qtemp + 1;
    end if;
  end if;
 end process;

this leads us to another problem: your counter signal has insufficient bits to hold 49,999,999 -> you need at least 26 bits
the UCF file has several errors:
1. NET "clk" ... has another signal name in comment
2. one signal can not have multiple locations
3. ON_BOARD_LED_output is a vector, so you should access each bit by using netname<index> and assign a location for each bit.
```
NET "ON_BOARD_LED_output<2>" LOC = "G1" ; # Bank = 3, Signal name = LD7
NET "ON_BOARD_LED_output<1>" LOC = "P4" ; # Bank = 2, Signal name = LD6
NET "ON_BOARD_LED_output<0>" LOC = "N4" ; # Bank = 2, Signal name = LD5
```
4. NET "output" ...: Why have you enabled internal pullup resistors (inside the IOB)? Most development boards have them externally.
5. and why are you limiting the current to 2 mA (DRIVE = 2)?
6. All pins have no assigned IOSTANDARD: This is needed for a proper timing analysis. If you want to switch to newer FPGAs and tools, it's then absolutely necessary to declare an IOSTANDARD