The goal is to drive a 47k load that requires at least 5mA of current. The design is as shown, with FET values matching their part number:
An LTSpice simulation (with generic pmos and nmos devices) demonstares that ideally the circuit should behave as follows when V1 is cycled from 0V to 8V:
Currently the voltage across the resistor remains at 300V even when the input is 0V. I've exchanged the pmos and it keeps the node at 0V but does not respond to a 5V input from V1.
I'm unsure as to what values R1 and R2 should have, originally they were both 100kOhm, or if there is something damaging the pmos that I have not considered. I haven't worked with such high voltages before and originally this circuit was designed for 5V (with R1=1k and R2=10k).
Best Answer
The P channel FET has a maximum gate-source voltage of +/- 20V so currently with resistor values as shown it will get 50V and die. Maybe a safer bet is the put a 12V zener across R2 to restrict this voltage under changing values of R1 - but don't lower R1 below 100k. 100k needs a 1W5 rated package - 300 x 300 / 100k = 0.9W.
I'd also be tempted to put something like 100 ohms in series with the P channel drain to limit current in case you have the 47k load resistor at some distance from that FET.