in my design a ispMACH 4032ZE CPLD (32Macrocells) operates as SPI slave driven by a moderate 8MHz master-clock. The part requires a 1.8V core supply drawing (estimated) tiny 100uA over the full temperature range according to the data sheet.
A well regulated 3.3V supply which is derived from the 6V…8.4V board supply via an LDO is available on the board. Since the CPLD is the only 1.8V part on the board a full-blown LDO regulator seems overkill and I wonder whether there are more cost- and/or space efficient solutions.
The board supply range of 6V…8.4V seemingly rules out most affordable dual output LDO regulators, even 1.8V zener diodes are similarly priced. (0.3€)
The most cost effective solution seems to be a resistor divider (1.8k/1.5) plus capacitor… however this seems somewhat wrong for a power rail.
Any comments?
Remark
I recognize that there are cheap LDOs that would easily satisfy my requirements and which I probably will use for the sake of predictability and robustness. Still, my question aimed at the slightly uncommon solutions such as using LEDs for voltage dropping.
Many thanks!
Best Answer
If you don't need much current, you can maybe use an LED? A red LED has a voltage drop about 1.5V, which will drop your 3.3 down to 1.8V. It seems weird to use a diode or LED to regulate power, but this FPGA development board which I've used, the XSA-50: http://www.xess.com/shop/product/xsa-50/ (click on manual to see the schematic) uses a 1N4148 to do exactly that (derive 2.5V from 3.3V). Also, free power indicator LED for the 1.8V rail.
The correct thing to do usually would be to use a Zener, like this one from digikey. But I kind of like the LED idea better, and you might have one lying around.