Electronic – Crosscoupling in SMPS PCB layout

Yes, there are stability issues and a brief moment when both FETs are on but the beauty of using a FET on the pull-down part of the circuit (i.e. a synchronous buck converter) instead of a schottky diode is this: -

1. Whatever duty cycle your PWM is the output voltage stays constant as a fraction of input voltage - you are in effect using the L and C on the output as a low pass filter to a square wave input.
2. Whatever load you have connected, providing the FETs are lowish on resistance, within reason you don't need to change the PWM mark-space ratio.
3. It will be more efficient on heavier loads than a non-synchronous buck regulator but the down-side is that on light loads it will be less efficient because you need current to drive the N channel FET because of gate capacitance.

I'd also advocate building a 555 timer sawtooth generator as the basis of your system. Something like this: -

I'd then feed it into a fast comparator and then the use the comparator output to drive the two FETs. The two FETs can be "time segregated" with a small RC time delay on the output of the comparator - the undelayed output and the delayed output would feed an AND gate for one of the gate drives and the the same for the other gate drive but using a NOR gate. Plan on maybe 50ns time delay introduced.

What you get is a half-decent synchronous buck convertor that just needs an input to the other comparator input to get the required duty cycle changes. OK so far? Then you can apply a simple control loop that lowers the 2nd input to the comparator as the input voltage gets bigger. Get this working and then apply another small control loop that actually regulates the PWM with load current changes a tad and this would probably work and no negative feedback involved.

Then, as the final touch, and with care and subtlety apply an overall control loop to keep the output better stabilized but remember, with a sync buck you can pretty much get half-decent stable performance without control loops that use negative feedback - if you are wanting to go this approach I can recommend it.

However, for me, I'd just call on Linear Technology and get the device that already does the job.

The large bodied capacitors should indeed avoid thermal relief unless absolutely necessary for manufacturability -- extra parasitics are not a good idea, and you will notice that the reference layout does not include them either. Thermals on the resistors are indeed a non-concern in this case, though -- their function is a low-current/low-noise one, and the extra resistance is insignificant compared to the resistors themselves.

The "Bottom Layer" on the reference board should be placed immediately adjacent to the top layer in your design -- this minimizes loop area and keeps outside traces from being coupled to. Other vacant inner layers under the DC/DC layout can be used for further thermal mass, while the bottom can be used for heatsink area. The feedback trace can go on any layer other than the top -- the reason why it isn't on top is to limit coupling to other critical nodes.