Electronic – Crystal Oscillator for STM32F407 with LAN8720

Circuits depicted by figures 3.8 & 3.9 actually work the same way, from the MAC's point of view. The only difference between them is the way the clock signal is generated for the PHY: 3.8 uses the internal crystal oscillator, 3.9 uses an external oscillator. Since 3.8 is demonstrated by the eval board of SMSC, I'd expect 3.9 to work as well.

However, there is a single note in the data sheet that you should pay attention to: "The REF_CLK Out Mode is not part of the RMII Specification. Timing in this mode is not compliant with the RMII specification. To ensure proper system operation, a timing analysis of the MAC and LAN8720 must be performed."

I have never tried to build a circuit with this PHY, so I don't know the exact implications of this note, but I'd expect the problem to lie in the fact that having a common, external oscillator being fed into both the MAC and the PHY can give you a controllable delay between them (you can play with the lengths of the two clock lines), but having the PHY sourcing the clock to the MAC will not give you this freedom, probably limiting the distance between them considerably.

Good questions.

1) Does REF_CLK must be routed without vias.

Whenever you see something like "must be routed without vias" without a good explanation, chances are that someone does not fully understand what is going on and just think that is a good idea.

One of several things may be the issue:

• Different trace impedance on different layers, which will cause reflections whenever there is a via.
• Reference plane problem, because the impedance between the power planes of the design is not low enough.

Both of these are easy to avoid and is good practice - often even required if you want to pass EMI tests, build a solid design etc.

So provided you do this, you can use vias without any issues. The faster the signals, the more careful you have to design the vias. I have previously written about how to design vias for 28+ GBps signals here.

2) Does REF_CLK need termination resistor?

Best thing to do here is a quick simulation with your favorite IBIS simulator - or have someone do that for you (sorry, these tools costs money - but are worth it).

If you have very fast edge rates, chances are you need a termination resistor if the trace is electrically longer than about 1/3 of the rise/fall time. Use simulation to be sure (unfortunately you did not provide enough information about your design, or I might just have done it right away).

3) Is 4mm difference in trace length @50Mhz acceptable?

Another good question. Look at the rise/fall times of your signal. If the electrical length of the rise/fall time is significantly longer than the trace length mismatch, this will work just fine. Actually it is a good practice not to overconstrain layouts, even though it is often possible to match trace lenghts within a very narrow tolerance.