Electronic – Current divider and capacitor

Copying the answer I gave when you posted the same question on Physics.SE:

I suppose that in this type of circuit the current and the voltage are in phase,

This question is asking for a transient solution, not an ac steady-state solution. So we can't really talk about the phase of the voltage or the current.

meaning that immediately after the switch is shut the current should be I=0?

This conclusion is incorrect.

Can't I just assume that the capacitor will be fully charged

No. It's explicitly stated in the problem, "For t<0 the switch is open and the capacitor is uncharged". The charge on a capacitor can not change instantaneously (when current is finite), so the charge on the capacitor is also 0 in the instant after the switch is closed.

A corollary that will help you solve this is that the voltage waveform across a capacitor is continuous.

I don't seem to find an approach getting expressions for the current and the charge after a very long time

The usual way to find the steady state dc response is to analyze the circuit in the dc regime, treating all capacitors as open circuits and all inductors as short circuits.

since U is constant, does that mean that the current is 0? Seems kind of unlikely.

No it's not unlikely. If the capacitor continued to accumulate charge after a long time, it's voltage would be increasing without bound, which would cause problems.

I'm supposed to set up a differential equation which then would give me a function with which I can find Q and I at certain points?

Start with

$$I_c = C\frac{\mathrm{d}V}{\mathrm{d}t}$$

and write \$I\$ in terms of other quantities you know (like the source voltage, the capacitor voltage, and the resistor values).

You don't tell us explicitly, but is seems that is some kind of homework or some textbook explanation. I guess that \$I\$ and \$I_L\$ are not the total currents in those branches, but only the transient components due to a surge in the current demand from the gate.

Of course the assumption is that all can be analyzed as a linear circuit, so that superimposition can be applied. In that case, you deactivate the battery, i.e. replace it with a short, and apply the current divider formula:

$$ I_1 = I_{tot} \dfrac{Z_2}{Z_1 + Z_2} $$

where you identify \$I\$ with \$I_{tot}\$, \$I_L\$ with \$I_1\$, \$Z_2 = \dfrac{1}{C s}\$ as the impedance of the capacitive branch and \$Z_1=R + L s\$ that of the inductive branch.

Then you get:

$$ I_L = I \dfrac{\dfrac{1}{C s}}{\dfrac{1}{C s} + R + L s} $$

which is the result you posted.

The fact that you can use superimposition is reasonable here, because you assume the transient doesn't make the gate change state, so that it can be assumed as a linear load. Whether this is a good assumption it depends on the situation in practice. But if my guess is right, i.e. an explanation coming from a textbook, this may be a simplifying assumption done to give you some clue about the phenomena that must be taken into account regarding chip supply bypassing. Take it as a first-order approximation, good if bypassing is done correctly. If bypass is so poor that a current surge from the chip makes it misbehave, well, in that case you are playing with a strongly non-linear situation, where pencil and paper calculations are less useful. A SPICE simulation with a good gate model could be much better in that case.