Electronic – Current limiter its not working as it should

The circuit shown will work, but the transistor and Rsense create a voltage drop that must be taken into account.
What you are seeing is the effect of this:

At 480mA the voltage drop across the 10Ω resistor would be 4.8V, which leaves no "room" for the transistor saturation voltage or the Rsense voltage drops.
So the current will be (Vsupply - Qsat - Vrsense) / Rload. To fix this, raise the supply by a couple of volts and try the 0Ω and 10Ω tests again. Also, lower Rdefend considerably (<10Ω)
You should hopefully see (almost) no difference.

For better results, the more gain you have the better. Another thing to note is (as Dave mentions in his answer) that Rbias needs to have a higher limiting point than the Rsense setting, otherwise it will dominate. If the transistor has a gain of 65, and you want Rsense set for 500mA, then Rbias must be set to allow more than 500mA. At 500Ω, it will set the absolute limit at 65 * ((5V - 1.4V) / 500Ω) = 468mA, so even if Rsense were set for 500mA you won't get it. To avoid this set Rbias for e.g. 250Ω, or as mentioned below use a MOSFET for Q1 and then the value isn't as important (10kΩ will do)

Another option is to use a common opamp constant current circuit:

Simulation with a supply of 4.8V, current limited to 500mA, Rload swept from 1mΩ to 50Ω and current through it plotted relative to this (note current stays flat at 500mA whilst limited):

This meets your requirements of a solid 500mA limiting at 4.8V supply, and is easily adjustable by varying the opamp non-inverting via input voltage R2/R3 divider. The formula is V(opamp+) / Rsense = I(Rload) For example, the 1V reference is divided by 20 to provide 50mV at the opamp+ input, so 50mV / 100mΩ = 500mA.
A MOSFET is used to avoid base current errors complicating matters (a MOSFET with low Vth can also be used in the original transistor circuit to improve things)

The problem is that the current thru M1 as a function of gate voltage is highly non-linear. At some point in the function, the gain is very high, which is making things unstable.

If you don't need high speed response from this circuit, you can dampen it somewhat past the point where you experimentally determine it won't oscillate at any operating point. To do that, add some resistance in series with the input signal going into the negative input of O1, then add some capacitance immediately between the O1 output and its negative input. Due to the non-linear nature of the current source this is driving, the capacitance value that guarantees no oscillation over any part of the operating range will also overdamp the system at others. That may be OK if you're not looking for fast response.

I would do the above anyway, but I wouldn't use a FET in the first place. You only need a 5 V compliance range (200 Ω times 25 mA), so you have plenty of voltage headroom. You have 24 V to start with. The load can take up to 5 V, and the current sense resistor another 2.5 V. That leaves 16.5 V headroom for the current source. You really don't need all that, but you can easily spend 5 V or so to get a reasonably linear current source.

Ditch the PFET and use a PNP transistor with 200 Ω or so in series with its emitter. The other end of the resistor is tied to the 24 V supply, the collector becomes the controlled current output, and the base is driven directly by the opamp output. This assumes the opamp output can swing to within half a volt of the positive supply, which many can't. The top schematic doesn't specify the opamp at all, and the bottom shows a TL082, which definitely can't get to within 500 mV of the top supply. Either use a opamp that can, or add a resistor divider between the opamp output and the transistor base so that the transistor is off with something the opamp can achieve. You can also add a diodes or even a zener in series with the emitter to drop the base voltage range if you need to.

With this scheme you still add the compensation cap as described earlier (it's usually a good idea to build that in anyway, you can always leave the cap off if you discover it's not needed), but the same value should apply well accross the whole operating range.

Another advantage of the PNP scheme is that much of the variations of the load are dealt with immediately by the transistor. The larger feedback loop then is mostly driven by the set point, and doesn't need to react as quickly to load changes. That allows more damping for more stability without sacrificing load regulation. It will slow down response to control inputs. From what you say, we don't know how important those two are and therefore how much this matters.

In general, you need to think about stability of circuits with feedback before building them and realizing they oscillate. The "Oh, crap" method of loop stability design is really not very good.