digital-logicflipfloplogic-gates
I've been looking at the circuit for the D flip flop with asynchronous reset and I do understand how the overall circuit works, but I can't understand what the point of connecting the wire in the red rectangle to the reset is.
The output will get reset if reset is set to 0 regardless of this connection.
Please correct me If I'm wrong.
You've been looking at incorrect components: D type flip-flop is used to sample the D input on each clock cycle, but you want to use load signal in order to enable sampling. Please note that the signal set which you wanted to use as load has different funtionality - it causes the output to go high (regardless of the value of D).
What you are looking for is D Flip-Flop with Enable. There are two simple approaches to add this functionality to a regular D-FF.
Feedback:
Adding a MUX which is controlled by Enable signal. On each clock edge the flop will either sample the new value, or the old value (which is equivalent to keeping an old value).
Clock gating:
Instead of MUXing the input to the flip-flop, you may simply disable the clock when you do not want to sample a new value. This approach is widely employed in order to reduce the power consumption (no clock -> no activity -> no active power consumed).
As pointed out by @Supercat in the comments, clock gating is the more sophisticated technique which requires a bit more expertise because it presents additional delays in clock path.
The only change that is required to convert your falling-edge triggered flip-flop to a rising-edge triggered flip-flop is to swap the true (non-inverted) clock and the inverted clock at the pins of your tri-state buffers and the transmission gate. For example, the center transmission gate in a rising-edge triggered flip-flop would have the true clock connected to the NMOS transistor and the inverted clock connected to the PMOS transistor.
By the way, near the middle left of your diagram you have a circled inverter that shows Q at its output and !Q at its input. That's correct...the output of the inverter just to the right of the circled inverter is !Q (Q-bar) rather than Q. If you follow the path from the D input through an inverting tristate buffer and the NOR gate you will see that the signal at the right end of the (non-inverting) transmission gate must have the same polarity as D, so that point in your circuit represents the true (non-inverted) Q value.
Best Answer
The wire in red is to make sure that the D input is overridden with a logic 0. This makes sure both sides of the master FF are reset at the same time. This also overrides the state of the clock input.
Now S and R will clear the slave latch so it is in the proper state. S is forced to '1' and R is forced to '0' at the same instant, thus Q is forced to '0' and Q\ is forced to '1' at the same instant. Q and Q\ can NEVER have the same state at the same time.
Since the rising edge of clock is used to load in the value at the D input which briefly causes both master R-S latches to toggle states (They are cross-wired so the value of D is sampled and locked into the latches in nanoseconds, or even picoseconds), both master R-S latches must be cleared at the same instant or a glitch could appear at R and S that briefly makes the slave latch put out glitches.
The operation of the reset pin should be clean and glitch free at the Q and Q\ outputs. If Q is set to 1 then a reset should clear it to 0 and Q\ becomes 1 with almost no skewing.
That is another reason for the extra reset connection. Data is supposed to be loaded in with almost no skewing in time between Q and Q\ changing states, so RESET has to work the same way, or downstream logic could be confused. These flip-flops are often used to sync data from a asynchronous source by using 2 in series with a common clock, so internally created glitches would never be tolerated. This could cause havoc and miss-counts in ripple-carry counters where many FF's are daisy-chained in a row.