Electronic – DDR software leveling

This is more of an "extended comment" than an answer, but let me start by saying no, I don't think you can debug this issue with such a limited set of test equipment. A person who has had a lot of experience doing these designs might be able to get some clues about what's going wrong using them, but I get the impression that you're not such a person.

For example, issues with risetime and ringing don't scale with clock frequency. If you can't see them at the high clock rate, you won't see them at the low clock rate, either.

The degree of success at this sort of thing depends on just how closely you duplicated the reference design — not just the schematic, but also the physical design, such as relative parts placement, PCB stackup, the routing and length-matching of traces, etc. Unless you know exactly what you're doing, you must match every detail of the reference design.

The fact that it does run at a lower clock rate suggests that you have issues with timing skews, possibly due to mismatched trace lengths, but also possibly due to mismatched terminations. You could verify this by renting the high-speed scope, but your time might be better spent getting started on a respin of the board right away.

Also, it's foolish to take a brand new board design and expect to boot a full-blown OS and application on it right away. You should always plan to develop (or find) some basic functional tests on individual functional units such as memory and communications interfaces.

These "hardware addressing" pins are not for addressing words in the RAM, but rather to select the address of the whole device on the IIC bus. The manufacturer realizes that you might want to have several of these chips on the same IIC bus, which means they each need a different IIC bus address. These pins allow you to pick one of 8 pre-defined addresses for each chip, depending on whether you tie these address lines high or low.

Some devices just use high and low on the address select pins. Other devices use high, low and open for trinary logic. 3 pins would give you 27 address possibilities. The TI INA219 only has two address select pins, but it uses 4-nary logic with high, low, connected to SDA or connected to SCL for a total of 16 address possibilities.