Electronic – Debounce slide switches in verilog

debouncefpgaverilog

I just created my first FPGA project. I created a small FPGA PCB with some slide switches to input values to the FPGA. Sadly, I did not debounce them properly with hardware, as you can see in these oscilloscope images:

osci_00
osci_01

How can I debounce the switches in "soft"ware on the FPGA? I found some examples online, but they didn't work for me. My internal clock is 16MHz.

Edit:
I am using a TinyFPGA Bx module. According to the datasheet, the inputs are built with Schmitt-Triggers. Looking at the images of the osci, those „steps“ are weird behaviors between slide switch and input. For hardware debouncing, I used a 10k resistor and 10n capacitor. The wierd voltage rise / fall creates some wierd Fpga behavior. Why could that be and how could one filter the signal to be „just one jump“?

Edit:
Solution: My clock was not unbounced. I solved it using Verilog.

Best Answer

I doubt you have issue in your Verilog code , and you say that weird behavior. The oscilloscope images seems normal. Try this simple example :

Switches to LEDs

`timescale 1ns / 1ps

module top(
    input [3:0] switches,
    output [3:0] leds
    );
    
    assign leds = switches;
endmodule

Remember to add constraint file for the switches and LEDs.

Still if you need to debounce switches, The easiest way to debounce switches / Push buttons in Verilog is to use Slow clock. In order to achieve a slow clock , you have to use a clock divider , divide your 16MHz clock into something slower like 8MHz or 4MHz. With a slower clock you'll be able to catch the event.

Read this Article

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