I have a schematic with decoupling capacitors that I do not know how to connect to the codec. They are not connected to the codec directly in the schematic as I assume that connecting them is a given for anyone who has studied electrical engineering (I am a chemical engineering student, this is my hobby).
Information about decoupling the codec, found in the data sheet:
My question:
How and where should the 3 caps (c53,54,78) be connected in relation to the IC ?
My thoughts:
It seems hat Filt+, AGND, VA, DGND are taken care of in the schematic. This leaves VL and VD. VD and Vl are parallel connected as described in the datasheet [ VD may be run from the systems logic supply (VL) ]. I have x2 0.1 uf and a 10 uf capacitor, the power inputs are parallel connected, so maybe I should arrange them in some special way…(?)
Any thoughts/comments would be greatly appreciated.
Best Answer
Decoupling caps are about low inductance, and inductance depends mostly on size. 100nF caps are used because they are cheap and small, but if your limit on capacitor size is what you are willing to solder, there is no reason to impose an artificially low limit on capacitance by using 100nF caps. So:
Think about the smallest package size you're comfortable soldering, say 0603.
Get the largest value in X7R/X5R 6.3V or 10V that will fit in 0603 (something like 10µF).
For power supplies VA VD VL: don't parallel ceramic caps, just use 10µF in 0603 package. Place them right at the pins with two ground vias on the cap. Since the power and ground pins are next to each other, just put the capacitor with its power and ground pads next to the corresponding pins, parallel to the chip. And put several ground vias on the cap. While you're at it, put a ground via below the chip on the heel of the pin too.
FILT+ is a voltage reference, so no big microphonic X7R cap. I'd use a 0603 polymer tantalum with 100nF MLCC in parallel. Put them next to each other, next to the chip, direct connection to FILT+ and AGND. Or an electrolytic instead of the tantalum, but it will take a lot of space near the chip so it could wreck your routing.
VQ1, I have no idea what it does, but parallelling 1µF and 100nF will only add resonance for no benefit, so just use one 1µF X7R MLCC.
C100/C101 should be low distortion types (ie, ceramic C0G not X7R).
You can add a low (but not too low) ESR electrolytic on VA.
If you put a ferrite bead on the 3V3 supply line (you should) then add the same electrolytic on the codec side to prevent the bead from ringing with the ceramic caps. Suggest BLM18EG601SN1D for bead.
Also I see 2 grounds in the schematic, it is not a good idea to use a split ground plane with these chips, it will only add more noise. Good placement and layout are much better.